Hello, This series updates the existing PHB4 model to the PHB5 spec. Also, a new testbench for PHB5 model is added, that does XSCOM read/writes to various registers of interest and verifies the values.
Thanking all the reviewers for their valuable comments! Testing ======== 1. Git tree for testing: https://gitlab.com/syedsaifabrar/qemu/tree/phb5v72 2. Gitlab pipeline: https://gitlab.com/syedsaifabrar/qemu/-/pipelines/3004770329 3. QEMU ppc64 functional tests: Ok: 15 Fail: 0 Skipped: 3 Changelog ========== v7 -> v7 RESEND: - Rebased to upstream commit 5624b266cdd513506fb333e9041778407b6d1ac4 - Resolved a merge conflict in PHB4 code. v6 -> v7: - Updates for clean-up related review comments - Tested with GitLab CI https://gitlab.com/syedsaifabrar/qemu/-/pipelines/2850120733/ v5 -> v6: - Separate reset and register read/write methods for PHB5. - PHB4 and PHB5 specific reset values. - Read/write logic for registers added to and removed in PHB5. v4 -> v5: - Rename qtest file and all methods to phb5. - New file for common defitions "pnv-qtest-common.h" - Initializing PnvPHB4Class members within class_init method. - Updated IODA3 PCT table max size to 128, each with 2 entries. - New macro for SCOM to PCBA address conversion. - Using be16_to_cpu as required. v3 -> v4: - Variables declaration moved to the top of the method pnv_phb4_reg_read() - Resolves the tsan build failure seen in https://gitlab.com/mstredhat/qemu/-/jobs/13201554945 v2 -> v3: - Added class size for PnvPHB4Class. - Updates for coding guidelines. v1 -> v2: - Added version check for PHB3 and PHB4 also. - Using the ResettableClass. - Reset of the root complex registers done in pnv_phb_root_port_reset_hold(). - New PnvPHB4Class to hold each register's RO mask. - Introduced method pnv_phb4_xsrc_reset(). v1: - Implemented sticky reset logic - Implemented read-only, write-only, W1C and WxC logic - Return all 1's on read to unimplemented registers - Update PCIE registers for link status, speed and width - Implement IODA PCT debug table without any functionality - Set write-mask bits for PCIE Link-Control-2 register that is read/written by PHB4 - Update LSI Source-ID register based on small/big PHB number of interrupts - New testbench for PHB4 model is added that does XSCOM read/writes to various registers of interest and verifies the values. Reviewed-by: Aditya Gupta <[email protected]> Reviewed-by: Michael Kowal<[email protected]> Regards. Saif Abrar (9): qtest/phb5: Add testbench for PHB pnv/phb5: Add reset logic to PHB5 pnv/phb5: Implement sticky reset logic in PHB5 pnv/phb5: Implement read-only and write-only bits of registers pnv/phb5: Implement write-clear and return 1's on unimplemented reg read pnv/phb5: Set link-active status in HPSTAT and LMR registers pnv/phb5: Set link speed and width in the DLP training control register pnv/phb5: Implement IODA PCT table pnv/phb5: Mask off LSI Source-ID based on number of interrupts hw/pci-host/pnv_phb.c | 20 +- hw/pci-host/pnv_phb4.c | 538 +++++++++++++++++++++++++--- hw/pci-host/pnv_phb4_pec.c | 2 +- hw/pci-host/pnv_phb5.c | 197 +++++++++- hw/pci-host/pnv_phb5_pec.c | 1 + hw/ppc/pnv.c | 1 + include/hw/pci-host/pnv_phb4.h | 43 ++- include/hw/pci-host/pnv_phb4_regs.h | 58 ++- include/hw/pci-host/pnv_phb5.h | 52 +++ tests/qtest/meson.build | 1 + tests/qtest/pnv-host-i2c-test.c | 13 +- tests/qtest/pnv-phb-test.c | 236 ++++++++++++ tests/qtest/pnv-qtest-common.h | 24 ++ tests/qtest/pnv-xive2-common.h | 7 +- 14 files changed, 1089 insertions(+), 104 deletions(-) create mode 100644 include/hw/pci-host/pnv_phb5.h create mode 100644 tests/qtest/pnv-phb-test.c create mode 100644 tests/qtest/pnv-qtest-common.h -- 2.52.0
