diff --git a/target/hexagon/gen_tcg_func_table.py
b/target/hexagon/gen_tcg_func_table.py
new file mode 100755
index 0000000000..ba56ede568
--- /dev/null
+++ b/target/hexagon/gen_tcg_func_table.py
@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import hex_common
+
+
+def main():
+ args = hex_common.parse_common_args(
+ "Emit the table of instruction translation functions"
+ )
+
+ with open(args.out, "w") as f:
+ f.write("#ifndef HEXAGON_FUNC_TABLE_H\n")
+ f.write("#define HEXAGON_FUNC_TABLE_H\n\n")
+ f.write("const SemanticInsn opcode_genptr[XX_LAST_OPCODE] = {\n")
+
+ for tag in hex_common.tags:
+ if hex_common.tag_ignore(tag):
+ continue
+ f.write(f" [{tag}] = generate_{tag},\n")
+
+ f.write("};\n\n")
+ f.write("#endif /* HEXAGON_FUNC_TABLE_H */\n")
+
+
+if __name__ == "__main__":
+ main()
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 61effa38cf..4305eda996 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -173,11 +173,7 @@ def main():
for tag in hex_common.tags:
if hex_common.tag_ignore(tag):
- f.write(f"static void generate_{tag}"
- f"(DisasContext *ctx)\n")
- f.write("{\n}\n\n")
continue
-
gen_def_tcg_func(f, tag, tagregs, tagimms)
f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n")
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index d0aabacf35..fd3f6a1edf 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -752,15 +752,6 @@ void gen_vframecheck(DisasContext *ctx, TCGv vsp)
tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], vsp);
}
-#ifndef CONFIG_HEXAGON_IDEF_PARSER
-static TCGv gen_slotval(DisasContext *ctx)
-{
- int slotval =
- (ctx->pkt.pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
- return tcg_constant_tl(slotval);
-}
-#endif
-
void gen_store32(TCGv vaddr, TCGv src, uint32_t width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
@@ -1855,8 +1846,4 @@ void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret,
TCGv_i64 a, TCGv_i64 b)
}
#include "tcg_funcs_generated.c.inc"
-const SemanticInsn opcode_genptr[XX_LAST_OPCODE] = {
-#define OPCODE(X) [X] = generate_##X
-#include "opcodes_def_generated.h.inc"
-#undef OPCODE
-};
+#include "tcg_func_table_generated.c.inc"
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 94e70b8657..a4807bed7b 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1520,7 +1520,8 @@ def helper_args(tag, regs, imms):
if need_slot(tag):
args.append(HelperArg(
"i32",
- "gen_slotval(ctx)",
+ "tcg_constant_i32((ctx->pkt.pkt_has_scalar_store_s1 & 1) | "
+ "(ctx->insn->slot << 1))",
"uint32_t slotval"
))
if need_part1(tag):
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index 0633852321..429317a658 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -42,10 +42,21 @@ hexagon_ss.add(semantics_generated)
#
# Step 2
# We use Python scripts to generate the following files
+# tcg_func_table_generated.c.inc
# printinsn_generated.h.inc
# op_attribs_generated.h.inc
# opcodes_def_generated.h.inc
#
+tcg_func_table_generated = custom_target(
+ 'tcg_func_table_generated.c.inc',
+ output: 'tcg_func_table_generated.c.inc',
+ depends: [semantics_generated],
+ depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
+ command: [python, files('gen_tcg_func_table.py'), semantics_generated,
+ gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h, '@OUTPUT@'],
+)
+hexagon_ss.add(tcg_func_table_generated)
+
printinsn_generated = custom_target(
'printinsn_generated.h.inc',
output: 'printinsn_generated.h.inc',
