Greetings,
This is rebased to 5624b266cdd513506fb333e9041778407b6d1ac4 and addressed
few remarks from Philippe Mathieu-Daudé which I resend the second time,
becaus ouriginal v5 sending was messed up by me and ignored by patchew.org
Sorry for the noise.
This series adds enough Cavium Octeon III CN73xx and EBB7304 board
support for upstream U-Boot 2026.04 to boot OpenBSD/octeon from USB
storage or through PCI e1000 and TFTP; the same machine also reaches
the prompt of the vendor U-Boot 2013.07 image from the Ubiquiti
EdgeRouter Infinity ER-8-XG recovery set. The model intentionally
covers the hardware exercised by these firmware and operating system
paths.
The vendor recovery image is U-Boot 2013.07, UBNT build
e1000_002_ef3a9; it reaches:
Octeon ubnt_e1000(Failsafe)#
This is the expected command prompt of the recovery U-Boot environment;
"Failsafe" describes the recovery image and does not indicate an
emulation or boot failure.
Early Octeon investigation used Amir Mehmood's original Octeon
host.patch as a behavioral reference; the basic machine approach and
several hardware model ideas come from that work. No code from that
patch remains in this implementation.
The series starts with three generic MIPS correctness fixes for MTTCG
interrupt state, MIPS64 segment checks, and architectural tlbwr
replacement semantics. It then adds Octeon CP0 state, the CN73xx CPU
model, PageMask handling, and unaligned accesses before introducing an
empty EBB7304 machine. The remaining patches add the machine state and
peripherals incrementally, followed by the functional test.
The machine currently models:
* the EBB7304 RAM layout, boot flash aliases, and boot-local RAM;
* CN73xx CPUs, Octeon CP0 state, CVMSEG, and configurable clocks;
* reset control, legacy CIU and CIU3 interrupt routing, mailboxes, and
secondary CPU release;
* UART, two TWSI controllers, synthesized DDR4 SPD, four LMC register
banks, fuses, RNG, POW, and the firmware probes used during platform
initialization;
* the EMM registers needed for firmware MMC initialization;
* two UCTL-wrapped DWC3 controllers, sufficient for U-Boot USB storage;
* a minimal PCIe host bridge, sufficient for a PCI e1000 device.
The functional test starts upstream U-Boot with four CPUs, enumerates
PCI, obtains a DHCP lease, downloads bsd.rd through user mode TFTP, and
boots the OpenBSD/octeon 7.9 installer.
The OpenBSD boot and USB stress testing requires additional patch for
xHCI which I haven't included into this series:
https://patchew.org/QEMU/[email protected]/
Each submitted commit was built in sequence and given the meaningful
smoke test available at that point. The final tree was tested with:
ninja -C build qemu-system-mips64
gmake -C build check-qtest-mips64
gmake -C build check-functional-mips64
The machine was used to build a few GCC build and full OpenBSD/octeon
release with LLVM inside OpenBSD/octeon using:
-m 32G -smp 8 -accel tcg,thread=multi
The longest non interrupted workload was near two weeks.
Known limitations are:
* native Octeon Ethernet is not modelled; the OpenBSD test uses PCI
e1000;
* EMM implements the firmware initialization path, not a complete MMC
data path;
* direct kernel boot through -kernel is not implemented;
* the newly modelled board and peripheral state lacks VMState
descriptions; migration and savevm are not expected to preserve the
complete machine state.
Patch layout:
1. target/mips: make CP0 interrupt state atomic
2. target/mips: fix MIPS64 segment access checks
3. target/mips: drop hidden TLB shadowing for tlbwr
4. target/mips: add Octeon CP0 register state
5. target/mips: add Octeon CN73xx CPU model
6. target/mips: pass env to compute_pagemask
7. target/mips: accept Octeon PageMask encodings
8. target/mips: allow Octeon unaligned accesses
9. hw/mips: add empty Octeon III machine
10. hw/mips: add Octeon CPUs and boot memory
11. hw/mips: add Octeon reset controller
12. hw/mips: add Octeon CIU3 CPU control
13. hw/mips: add Octeon CIU3 interrupt routing
14. hw/mips: add Octeon legacy CIU
15. hw/mips: add Octeon CSR window
16. hw/mips: expose Octeon reset CSRs
17. hw/mips: add Octeon MIO boot support
18. hw/mips: wire the Octeon UART
19. hw/i2c: add Octeon TWSI controller
20. hw/mips: add Octeon EMM controller
21. hw/mips: add Octeon LMC controllers
22. hw/mips: add Octeon boot support registers
23. hw/usb: add Octeon USB controller
24. hw/pci-bridge: add Octeon PCI host bridge
25. hw/pci-bridge: add Octeon PCI memory window
26. tests/functional: test Octeon III boot
