From: Nicolas Pitre <[email protected]> Define structs to represent the hardware capabilities of capacity and bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI).
Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Radim Krčmář <[email protected]> Signed-off-by: Drew Fustini <[email protected]> --- MAINTAINERS | 7 +++++ include/hw/riscv/cbqri.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4ca1751e30f5..2984779ce43a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -403,6 +403,13 @@ F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc F: disas/riscv-xventana* +RISC-V QoS (Ssqosid ext and CBQRI spec) +M: Nicolas Pitre <[email protected]> +M: Drew Fustini <[email protected]> +L: [email protected] +S: Supported +F: include/hw/riscv/cbqri.h + RISC-V SiFive (Xsf*) extensions M: Max Chou <[email protected]> L: [email protected] diff --git a/include/hw/riscv/cbqri.h b/include/hw/riscv/cbqri.h new file mode 100644 index 000000000000..1b3d85973717 --- /dev/null +++ b/include/hw/riscv/cbqri.h @@ -0,0 +1,66 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RISCV_CBQRI_H +#define HW_RISCV_CBQRI_H + +#include "qemu/typedefs.h" + +#define RISCV_CBQRI_VERSION_MAJOR 1 +#define RISCV_CBQRI_VERSION_MINOR 0 + +#define TYPE_RISCV_CBQRI_CC "riscv.cbqri.capacity" +#define TYPE_RISCV_CBQRI_BC "riscv.cbqri.bandwidth" + +/* Capacity Controller hardware capabilities */ +typedef struct RiscvCbqriCapacityCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t ncblks; + + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + bool supports_alloc_op_flush_rcid:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_occupancy:1; +} RiscvCbqriCapacityCaps; + +/* Bandwidth Controller hardware capabilities */ +typedef struct RiscvCbqriBandwidthCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_rdwr_count:1; + bool supports_mon_evt_id_rdonly_count:1; + bool supports_mon_evt_id_wronly_count:1; +} RiscvCbqriBandwidthCaps; + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps); +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps); +#endif -- 2.43.0
