On Fri, 16 Oct 2026 17:46:55 +0800 Jinjie Ruan <[email protected]> wrote:
> From: Jonathan Cameron <[email protected]> > > Add the MPAM system registers for TCG: MPAMIDR_EL1 (RO) reporting 64 > PARTIDs and 4 PMGs, and MPAM0_EL1/MPAM1_EL1 (RW, of which only > MPAM1_EL1.MPAMEN is architecturally reset). Advertise FEAT_MPAM via > ID_AA64PFR0.MPAM for TCG CPUs. > > It is common to support MPAM on CPU cores, but not in the rest of the > system, so there is little disadvantage in always enabling these. > > Based on an RFC series by Jonathan Cameron, adapted to the current > idregs[] storage and access_tid3() naming. > > Signed-off-by: Jonathan Cameron <[email protected]> Definitely wouldn't trust this guy :) He took a few naughty short cuts. > Signed-off-by: Jinjie Ruan <[email protected]> > diff --git a/target/arm/helper.c b/target/arm/helper.c > index ff0b766..896ac0e 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6907,6 +6907,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_tid3, > .resetvalue = cpu->isar.mvfr0 }, > + { .name = "MPAMIDR_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 0, .crn = 0xa, .crm = 4, .opc2 = 4, > + .access = PL1_R, .type = ARM_CP_CONST, > + .accessfn = access_tid3, > + .resetvalue = cpu->isar.mpamidr_el1 }, > + { .name = "MPAM0_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 0, .crn = 0xa, .crm = 5, .opc2 = 1, > + .access = PL1_RW, .type = ARM_CP_ALIAS, Similar to patch 2 (I reviewed them backwards) not sure why I ever set this to ARM_CP_ALIAS. > + .accessfn = access_tid3, Never trust code I bodged years ago :( Wrong trap. Now you have the appropriate EL2 registers in next patch should use a trap on the relevant bits being set there. Will want to swap the patches around for that to work I think. Also possibly needs the EL3 trap register defined. > + .fieldoffset = offsetof(CPUARMState, mpam0_el1), > + }, > + { .name = "MPAM1_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 0, .crn = 0xa, .crm = 5, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_ALIAS, > + .accessfn = access_tid3, > + .fieldoffset = offsetof(CPUARMState, mpam1_el1), > + }, > { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, > .access = PL1_R, .type = ARM_CP_CONST,
