On Fri, 16 Oct 2026 17:47:02 +0800 Jinjie Ruan <[email protected]> wrote:
> From: Jonathan Cameron <[email protected]> > > Add the mpam-msc-cache subtype for cache components, with the > cache-level/cache-type/cpu properties the board uses to place the > MSC in the cache topology. Its realize assembles the cache > identity view of MPAMF_IDR (same as the memory side, plus SP4=0 > for RME) and IIDR/AIDR; the CPOR/CCAP/PRI feature bits arrive > with their respective partitioning patches. > > Based on an RFC series by Jonathan Cameron. > > Signed-off-by: Jonathan Cameron <[email protected]> > Signed-off-by: Jinjie Ruan <[email protected]> Very similar comments to previous as you might expect. > --- > hw/arm/mpam.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > > diff --git a/hw/arm/mpam.c b/hw/arm/mpam.c > index 8a85c3b..17ca286 100644 > --- a/hw/arm/mpam.c > +++ b/hw/arm/mpam.c > @@ -264,11 +264,22 @@ typedef struct MPAMMSCMemState { > MPAMMSCState parent; > } MPAMMSCMemState; > > +typedef struct MPAMMSCCacheState { > + MPAMMSCState parent; > + uint8_t cache_level; > + uint8_t cache_type; > + uint16_t cpu; > + > +} MPAMMSCCacheState; > + > DECLARE_INSTANCE_CHECKER(MPAMMSCState, MPAM_MSC_DEVICE, TYPE_MPAM_MSC); > > DECLARE_INSTANCE_CHECKER(MPAMMSCMemState, MPAM_MSC_MEM_DEVICE, > TYPE_MPAM_MSC_MEM); > > +DECLARE_INSTANCE_CHECKER(MPAMMSCCacheState, MPAM_MSC_CACHE_DEVICE, > + TYPE_MPAM_MSC_CACHE); > + > static uint64_t mpam_msc_read_reg(void *opaque, hwaddr offset, > unsigned size) > { > @@ -420,12 +431,72 @@ static void mpam_msc_mem_realize(DeviceState *dev, > Error **errp) > } > } > > +static void mpam_msc_cache_realize(DeviceState *dev, Error **errp) > +{ > + MPAMMSCState *s = MPAM_MSC_DEVICE(dev); > + int i; > + > + mpam_msc_realize(dev, errp); > + > + for (i = 0; i < s->num_ris; i++) { for (int i = 0;... > + Mpamf *mpamf = &s->mpamf[i]; > + > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, PART_ID_MAX, > + s->num_partid - 1); > + /* No PCMG for now */ > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, PMG_MAX, 0); > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, EXT, 1); > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_RIS, s->num_ris > > 1); > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, RIS_MAX, > + s->num_ris > 1 ? s->num_ris - 1 : 0); > + > + /* Optional - test with and without */ Same as before. > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_ESR, 1); > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_EXTD_ESR, > + s->num_ris > 1); > + > + /* We won't implement any implementation specific stuff */ > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, NO_IMPL_PART, 1); > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, NO_IMPL_MSMON, 1); > + > + /* Need to implement for RME */ > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, SP4, 0); > + > + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_PARTID_NRW, > + s->num_int_partid < s->num_partid); > + > + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, IMPLEMENTER, > + MPAM_IIDR_IMPLEMENTER); > + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, REVISION, 0); > + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, VARIANT, 0); > + /* FIXME get allocation for this emulation */ Follow through from previous. > + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, PRODUCT_ID, 42); > + > + mpamf->aidr = FIELD_DP32(mpamf->aidr, MPAMF_AIDR, ARCH_MINOR_REV, 1); > + mpamf->aidr = FIELD_DP32(mpamf->aidr, MPAMF_AIDR, ARCH_MAJOR_REV, 1); > + > + if (s->num_int_partid < s->num_partid) { > + mpamf->partid_nrw_idr = FIELD_DP32(mpamf->partid_nrw_idr, > + MPAMF_PARTID_NRW_IDR, > + INTPARTID_MAX, > + s->num_int_partid - 1); > + } > + /* TODO: Initialize all on as if firmware had done it for us */ > + } > +}
