On Fri, 16 Oct 2026 17:47:06 +0800 Jinjie Ruan <[email protected]> wrote:
> From: Jinjie Ruan <[email protected]> > > Add the memory-bandwidth controls: MPAMF_MBW_IDR (16-bit BWA_WD > fraction, MIN/MAX/PBM/PROP support, BWPBM_WD = MPAM_MBW_PART) > with HAS_MBW_PART on the memory subtype, and read/write handling > for MBW_MIN, MBW_MAX, MBW_PROP and the MBW_PBM bitmap per > selected internal PARTID. > > Note the MBW_MIN write mask check references the CMIN mask -- > a leftover fixed later by the CMIN/CASSOC patch. > > Signed-off-by: Jinjie Ruan <[email protected]> I'm a bit amused that the Todo from my RFC is still here and not fixed. Needs doing. > --- > hw/arm/mpam.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/hw/arm/mpam.c b/hw/arm/mpam.c > index 2b1401e..7c33ec4 100644 > --- a/hw/arm/mpam.c > +++ b/hw/arm/mpam.c > case A_MPAMF_MPAMCFG_CPBM0... > (A_MPAMF_MPAMCFG_CPBM0 + ((MPAM_CACHE_PART + 31) / 32 - 1) * 4): > { > @@ -445,6 +490,22 @@ static void mpam_msc_write_reg(void *opaque, hwaddr > offset, uint64_t value, > mpamf->per_nrw_id[nrw_part_sel].cfg_cpbm[array_offset] = value; > return; > } > + case A_MPAMF_MPAMCFG_MBW_PBM0... > + (A_MPAMF_MPAMCFG_MBW_PBM0 + ((MPAM_MBW_PART + 31) / 32 - 1) * 4): > + { > + uint32_t array_offset; > + > + if (!FIELD_EX32(mpamf->idr, MPAMF_IDR, HAS_MBW_PART)) { > + qemu_log_mask(LOG_UNIMP, > + "MPAM: Unexpected write to MBW_PBM when > !HAS_MBW_PART\n"); > + return; > + } > + /* TODO: Figure out write mask to check this stays in write bits */ Indeed that needs doing. Wasn't I lazy in that RFC? :) > + array_offset = (offset - A_MPAMF_MPAMCFG_MBW_PBM0) / > sizeof(uint32_t); > + > + mpamf->per_nrw_id[nrw_part_sel].cfg_mbw_pbm[array_offset] = value; > + return; > + }
