On Fri, 16 Oct 2026 17:47:08 +0800 Jinjie Ruan <[email protected]> wrote:
> From: Jinjie Ruan <[email protected]> > > Add the cache-capacity controls: MPAMF_CCAP_IDR (4-bit CMAX/CASSOC > band widths, HAS_CMIN/HAS_CASSOC advertised ahead of their storage, bandwidths > CMAX soft-limit support) with HAS_CCAP_PART on the cache subtype, > and read/write handling for MPAMCFG_CMAX per selected internal > PARTID, guarded on CCAP support. > > Signed-off-by: Jinjie Ruan <[email protected]> One trivial inline otherwise fine Reviewed-by: Jonathan Cameron <[email protected]> > --- > hw/arm/mpam.c | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > @@ -701,6 +724,20 @@ static void mpam_msc_cache_realize(DeviceState *dev, > Error **errp) > mpamf->pri_idr = FIELD_DP32(mpamf->pri_idr, MPAMF_PRI_IDR, > INTPRI_WD, 2); > > + /* Capacity Partitioning */ > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + HAS_CMAX_SOFTLIM, 1); > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + NO_CMAX, 0); > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + HAS_CMIN, 1); > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + HAS_CASSOC, 1); > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + CASSOC_WD, 4); /* Not much flex on this > */ Any idea what I meant by that comment? I've no idea. Probably drop it - it might just have been me musing about the MPAM spec. > + mpamf->ccap_idr = FIELD_DP32(mpamf->ccap_idr, MPAMF_CCAP_IDR, > + CMAX_WD, 4); > + > if (s->num_int_partid < s->num_partid) { > mpamf->partid_nrw_idr = FIELD_DP32(mpamf->partid_nrw_idr, > MPAMF_PARTID_NRW_IDR,
