On Fri, 16 Oct 2026 18:10:49 +0800 Jinjie Ruan <[email protected]> wrote:
> From: Jinjie Ruan <[email protected]> > > Give the cache MSCs their CSU model capacity: 512 KiB for L2 and > 32 MiB for L3, matching the cache sizes guests infer from the > topology, so the occupancy snapshot reads back realistic values. Read them from the system registers like we do for PPTT. Jonathan > > Signed-off-by: Jinjie Ruan <[email protected]> > --- > hw/arm/virt.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index a57ba56..1bcdd20 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -2192,6 +2192,10 @@ static void create_mpam_msc_cache(VirtMachineState > *vms, int level, > object_property_set_uint(OBJECT(dev), "cache-type", UNIFIED_CACHE, > &error_fatal); > object_property_set_uint(OBJECT(dev), "cpu", i, &error_fatal); > + /* Occupancy model: usage = capacity scaled by the CPBM fraction */ > + object_property_set_uint(OBJECT(dev), "csu-capacity-bytes", > + level == 2 ? 512 * KiB : 32 * MiB, > + &error_fatal); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, *base); > *base += MPAM_SIZE;
