On Wed, 04 Nov 2026 16:34:35 +0000 Jim MacArthur <[email protected]> wrote:
> These were introduced in the PCIe Root registers patch series, but need to be > duplicated for the ICH9 driver patch. > > Signed-off-by: Jim MacArthur <[email protected]> > --- > hw/pci/pcie.c | 15 +++++++++++++++ > include/hw/pci/pcie.h | 2 ++ > include/hw/pci/pcie_regs.h | 4 ++++ > 3 files changed, 21 insertions(+) > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index bd00305ecc..7dfb0af801 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -1389,6 +1389,21 @@ uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev) > return pci_get_long(dev->config + dev->exp.pri_cap + PCI_PRI_ALLOC_REQ); > } > > +/* IDE (Integrity & Data Encryption) */ > +void pcie_ide_init(PCIDevice *dev, uint16_t offset) > +{ > + pcie_add_capability(dev, PCI_EXT_CAP_ID_IDE, PCI_IDE_VER, > + offset, PCI_IDE_SIZEOF); > + uint32_t cap = PCI_IDE_CAP_SELECTIVE; I'd add a blank line here. Also that local variable for cap isn't adding any value to my eyes. pci_set_byte(dev->config + offset + PCI_IDE_CAP, PCI_IDE_CAP_SELECTIVE); This is very minimalist but seems otherwise valid - 1 stream =m bi address association register blocks etc given zeros in the various other capabilities. I sort of feel like it would make sense to set those zeros explicitly here just act as documentation but I guess that's not strictly required. > + pci_set_byte(dev->config + offset + PCI_IDE_CAP, cap); > +} > + > +void pcie_cap_tee_init(PCIDevice *dev) > +{ > + pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + > PCI_EXP_DEVCAP, > + PCI_EXP_DEVCAP_TEE); > +} > + > bool pcie_pri_enabled(const PCIDevice *dev) > { > if (!pci_is_express(dev) || !dev->exp.pri_cap) { > diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h > index ec25e7a7de..bdebbfffe9 100644 > --- a/include/hw/pci/pcie.h > +++ b/include/hw/pci/pcie.h > @@ -161,6 +161,8 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, > uint8_t pasid_width, > bool exec_perm, bool priv_mod); > void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t > outstanding_pr_cap, > bool prg_response_pasid_req); > +void pcie_ide_init(PCIDevice *dev, uint16_t offset); > +void pcie_cap_tee_init(PCIDevice *dev); > > uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev); > bool pcie_pri_enabled(const PCIDevice *dev); > diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h > index 33a22229fe..5f527abf35 100644 > --- a/include/hw/pci/pcie_regs.h > +++ b/include/hw/pci/pcie_regs.h > @@ -182,4 +182,8 @@ typedef enum PCIExpLinkWidth { > #define PCI_DOE_VER 0x1 > #define PCI_DOE_SIZEOF 24 > > +/* IDE Fields */ > +#define PCI_IDE_VER 0x1 > +#define PCI_IDE_SIZEOF 12 I'd add something on what options you are enabling for that size given variable length nature of that structure. From a quick look at the spec this seems short given CAP_SELECTIVE is set but maybe I can't count. The spec is a little confusing wrt to the count field being 0 means 1 is available vs the need for the Selective IDE Stream Register block but I'm fairly sure you need one of those after the fixed header chunk. > + > #endif /* QEMU_PCIE_REGS_H */ >
