On Thu, 29 Oct 2026 15:05:11 +0000 Jim MacArthur <[email protected]> wrote:
> From: Pierrick Bouvier <[email protected]> > > Adds the TEE flag in the legacy config space, and the IDE > (Integrity & Data Encryption) extended capability. These > will be present when rme-cap=on is specified for the > pcie-root-port device. > > Signed-off-by: Pierrick Bouvier <[email protected]> > Signed-off-by: Jim MacArthur <Jim [email protected]> > --- > hw/pci-bridge/gen_pcie_root_port.c | 21 ++++++++++++++++++++- > hw/pci/pcie.c | 19 +++++++++++++++++++ > include/hw/pci/pcie.h | 3 +++ > include/hw/pci/pcie_regs.h | 4 ++++ > 4 files changed, 46 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-bridge/gen_pcie_root_port.c > b/hw/pci-bridge/gen_pcie_root_port.c > index 5434d693d9..ab8087da87 100644 > --- a/hw/pci-bridge/gen_pcie_root_port.c > +++ b/hw/pci-bridge/gen_pcie_root_port.c > @@ -26,13 +26,16 @@ OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, > GEN_PCIE_ROOT_PORT) > #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 > #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ > (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) > - > +#define GEN_PCIE_ROOT_PORT_ACS_END \ > + (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) Can't you figure this out from root port class acs offset? Or if you want it in a fixed place follow that pattern and stash it in the root class during dev_rp_dev_class_init. > #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 > #define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096 > > struct GenPCIERootPort { > /*< private >*/ > PCIESlot parent_obj; > + bool rme_caps; > + > /*< public >*/ > > /* additional resources to reserve */ > @@ -71,6 +74,7 @@ static void gen_rp_realize(DeviceState *dev, Error **errp) > GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d); > PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); > Error *local_err = NULL; > + uint32_t next_cap_offset = GEN_PCIE_ROOT_PORT_ACS_END; > > rpc->parent_realize(dev, &local_err); > if (local_err) { > @@ -100,6 +104,19 @@ static void gen_rp_realize(DeviceState *dev, Error > **errp) > d->wmask[PCI_IO_BASE] = 0; > d->wmask[PCI_IO_LIMIT] = 0; > } > + > + if (grp->rme_caps) { Not arm specific. Can't see any harm in using a generic config name for this. Actually I'm not seeing a reason not to always include the ide cap. Maybe less so for setting up tee. Haven't really thought about that. > + pcie_ide_init(d, next_cap_offset); > + > + /* Unused value, but may be useful for the next capability */ > + next_cap_offset += PCI_IDE_SIZEOF; > + > + /* > + * Set up TEE (in the legacy config space, not an extended > + * capability) > + */ > + pcie_cap_tee_init(d); > + } > } > > static const VMStateDescription vmstate_rp_dev = { > @@ -133,6 +150,8 @@ static const Property gen_rp_props[] = { > speed, PCIE_LINK_SPEED_16), > DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > width, PCIE_LINK_WIDTH_32), > + DEFINE_PROP_BOOL("rme-caps", GenPCIERootPort, > + rme_caps, false), > }; > > static void gen_rp_dev_class_init(ObjectClass *klass, const void *data) > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 42c4997b42..bf2c184cfc 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c
