From: Manish Honap <[email protected]> Assign 1b36:0017 to the CXL Type-2 device added later in this series, and add the processing accelerator class code 0x1200.
The CXL memory device class 0x0502 with programming interface 0x10 would bind the guest cxl_pci driver, which treats the device as a Type-3 memory expander. AI-used-for: code (prototype) Signed-off-by: Manish Honap <[email protected]> --- docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_ids.h | 3 +++ 3 files changed, 6 insertions(+) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index 74460bb19e..1443830ad1 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -109,6 +109,8 @@ PCI devices (other than virtio): PCIe Upstream Switch Port (``-device pcie-upstream-port``) 1b36:0016 PCIe Downstream Switch Port (``-device pcie-downstream-port``) +1b36:0017 + CXL Type-2 device (``-device cxl-type2``) All these devices are documented in :doc:`index`. diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 359331102f..4ca1548771 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -123,6 +123,7 @@ extern bool pci_available; #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 #define PCI_DEVICE_ID_REDHAT_PCIE_USP 0x0015 #define PCI_DEVICE_ID_REDHAT_PCIE_DSP 0x0016 +#define PCI_DEVICE_ID_REDHAT_CXL_TYPE2 0x0017 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 #define FMT_PCIBUS PRIx64 diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 477609ed62..c35b7b99db 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -154,6 +154,9 @@ #define PCI_CLASS_SP_MANAGEMENT 0x1120 #define PCI_CLASS_SP_OTHER 0x1180 +#define PCI_BASE_CLASS_ACCELERATOR 0x12 +#define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200 + #define PCI_CLASS_OTHERS 0xff /* Vendors and devices. Sort key: vendor first, device next. */ -- 2.53.0
