From: Frédéric Pétrot <[email protected]> Addition of the interrupt flags of the cause registers into machine migration state.
Signed-off-by: Frédéric Pétrot <[email protected]> --- target/riscv/machine.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 0de06e9588..080a983a19 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -114,6 +114,7 @@ static const VMStateDescription vmstate_hyper = { VMSTATE_UINT64(env.vsscratch, RISCVCPU), VMSTATE_UINT64(env.vsepc, RISCVCPU), VMSTATE_UINT64(env.vscause, RISCVCPU), + VMSTATE_UINT64(env.vscause_int, RISCVCPU), VMSTATE_UINT64(env.vstval, RISCVCPU), VMSTATE_UINT64(env.vsatp, RISCVCPU), VMSTATE_UINT16(env.vsiselect, RISCVCPU), @@ -126,6 +127,7 @@ static const VMStateDescription vmstate_hyper = { VMSTATE_UINT64(env.sscratch_hs, RISCVCPU), VMSTATE_UINT64(env.sepc_hs, RISCVCPU), VMSTATE_UINT64(env.scause_hs, RISCVCPU), + VMSTATE_UINT64(env.scause_int_hs, RISCVCPU), VMSTATE_UINT64(env.stval_hs, RISCVCPU), VMSTATE_UINT64(env.satp_hs, RISCVCPU), VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), @@ -615,9 +617,11 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.stvec, RISCVCPU), VMSTATE_UINT64(env.sepc, RISCVCPU), VMSTATE_UINT64(env.scause, RISCVCPU), + VMSTATE_UINT64(env.scause_int, RISCVCPU), VMSTATE_UINT64(env.mtvec, RISCVCPU), VMSTATE_UINT64(env.mepc, RISCVCPU), VMSTATE_UINT64(env.mcause, RISCVCPU), + VMSTATE_UINT64(env.mcause_int, RISCVCPU), VMSTATE_UINT64(env.mtval, RISCVCPU), VMSTATE_UINT16(env.miselect, RISCVCPU), VMSTATE_UINT16(env.siselect, RISCVCPU), -- 2.43.0
