Fabrice Bellard a écrit : > Aurelien Jarno wrote: >> Hi, >> >> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr, >> sdl and sdr instructions are not correctly implemented. In case of >> exception the BadVAddr register gets the aligned address instead of the >> unaligned original address. >> >> In addition to that, the store instructions are generating the wrong >> exception, AdEl instead of AdEs, because the current implementation >> first do a load. >> >> The patch below fixes that by accessing the bytes one by one, starting >> by the unaligned original address. >> >> Bye, >> Aurelien > > [...] > > BTW, you could simplify a lot the implementation : > > switch (GET_LMASK(T0)) { > case 0: > T0 = (int32_t)tmp; > break; > case 1: > T0 = (int32_t)((tmp << 8) | (T1 & 0x000000FF)); > break; > case 2: > T0 = (int32_t)((tmp << 16) | (T1 & 0x0000FFFF)); > break; > case 3: > T0 = (int32_t)((tmp << 24) | (T1 & 0x00FFFFFF)); > break; > } > > -> > > v = GET_LMASK(T0); > if (v == 0) { > T0 = tmp; > } else { > TO = (int32_t)((tmp << (8 * v)) | (T1 & ((1 << (v * 8)) - 1))); > } >
Agreed, but this code is actually removed and not added by the patch I posted. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [EMAIL PROTECTED] | [EMAIL PROTECTED] `- people.debian.org/~aurel32 | www.aurel32.net