Aurelien Jarno a écrit :
Maybe. The CPU probes for cacheline size, checks for errata #42 vs #45, reads debug registers, attempts to identify the bus speed by comparing I/O access times, tries to verify the system using a TPM and fails all cases. What can you do?Emulate a simpler architecture like mips or arm? ;-)
I don't think ARM qualifies as a simple architecture, it certainly
isn't in the same league as MIPS, at least not ARMv6 and ARMv7 :)
Laurent
