Alan Cox a écrit : >> Well on real hardware, the instruction rate and the timer are linked: >> the timer run at half the speed of the CPU. As the corresponding >> assembly code is very small, only uses registers and is run in kernel >> mode, you know for sure that 48 cycles is more than enough. > > What happens on NMI or if you take an ECC exception and scrubbing stall > off the memory controller while loading part of that cache line of code > into memory ? >
The code returns -ETIME, and the function is run again with the minimum delay. So as long as you don't have an exception every time, the code works. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [EMAIL PROTECTED] | [EMAIL PROTECTED] `- people.debian.org/~aurel32 | www.aurel32.net
