On 2012-09-10 11:18, Avi Kivity wrote: > On 09/10/2012 12:09 PM, Jan Kiszka wrote: >> On 2012-09-10 10:56, Avi Kivity wrote: >>> On 09/10/2012 04:27 AM, Matthew Ogilvie wrote: >>>> Intel's definition of "edge triggered" means: "asserted with a >>>> low-to-high transition at the time an interrupt is registered and >>>> then kept high until the interrupt is served via one of the >>>> EOI mechanisms or goes away unhandled." >>>> >>>> So the only difference between edge triggered and level triggered >>>> is in the leading edge, with no difference in the trailing edge. >>> >>> Hard to believe. So an edge while cpu interrupts are disabled is ignored? >> >> No, this is about the PIC, not the CPU interrupt inputs. > > I see, the interrupt is still sent to the processor; but IRR reflects > that status of the input line, not a "pending interrupt" status. > > Will this survive live migration? If we clear IRR, then we must rely on > the other end to remember the IRQ, but if processor interrupts are > disabled there won't be an INTACK and the signal is lost.
We clear the IRR as there is nothing to deliver to the CPU anymore. No IRQ source will drop its line as long as there is a reason for the IRQ, I checked the edge-using devices. So we can't lose anything. Jan
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