> -----Original Message-----
> From: qemu-devel-bounces+ericj=mips....@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips....@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Thursday, September 06, 2012 2:11 AM
> To: Jia Liu
> Cc: qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v7 04/14] target-mips-ase-dsp: Add branch
> instructions
>
> On Tue, Aug 28, 2012 at 02:36:15PM +0800, Jia Liu wrote:
> > Add MIPS ASE DSP Branch instructions.
> >
> > Signed-off-by: Jia Liu <pro...@gmail.com>
> > ---
> > target-mips/translate.c | 50
> +++++++++++++++++++++++++++++++++++++++++++----
> > 1 file changed, 46 insertions(+), 4 deletions(-)
> >
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index e1ea9c1..18d827d 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -332,6 +332,14 @@ enum {
> > OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
> > };
> >
> > +/* MIPS DSP REGIMM opcodes */
> > +enum {
> > + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
> > +#if defined(TARGET_MIPS64)
> > + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
> > +#endif
> > +};
> > +
> > /* Coprocessor 0 (rs field) */
> > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
> >
> > @@ -2841,6 +2849,22 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
> > }
> > btgt = ctx->pc + insn_bytes + offset;
> > break;
> > + case OPC_BPOSGE32:
> > +#if defined(TARGET_MIPS64)
> > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> > +#else
> > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
> > +#endif
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > +#if defined(TARGET_MIPS64)
> > + case OPC_BPOSGE64:
> > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > +#endif
>
> For this part of the code, BPOSGE32 is basically the same than BPOSGE64.
> Therefore this can be written the following way:
>
> | case OPC_BPOSGE32:
> | #if defined(TARGET_MIPS64)
> | case OPC_BPOSGE64:
> | tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> | #else
> | tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
> | #endif
> | bcond_compute = 1;
> | btgt = ctx->pc + insn_bytes + offset;
> | break;
>
> > case OPC_J:
> > case OPC_JAL:
> > case OPC_JALX:
> > @@ -3029,6 +3053,16 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
> > tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
> > MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
> > goto likely;
> > + case OPC_BPOSGE32:
> > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
> > + MIPS_DEBUG("bposge32 %s, " TARGET_FMT_lx, t0, btgt);
> > + goto not_likely;
> > +#if defined(TARGET_MIPS64)
> > + case OPC_BPOSGE64:
> > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
> > + MIPS_DEBUG("bposge64 %s, " TARGET_FMT_lx, t0, btgt);
> > + goto not_likely;
> > +#endif
> > case OPC_BLTZALS:
> > case OPC_BLTZAL:
> > ctx->hflags |= (opc == OPC_BLTZALS
> > @@ -11284,10 +11318,6 @@ static void decode_micromips32_opc (CPUMIPSState
> *env, DisasContext *ctx,
> > (ctx->opcode >> 18) & 0x7, imm << 1);
> > *is_branch = 1;
> > break;
> > - case BPOSGE64:
> > - case BPOSGE32:
> > - /* MIPS DSP: not implemented */
> > - /* Fall through */
>
> I don't think this is correct. These are for microMIPS, and AFAIK, DSP
> ASE instructions can be encoded using microMIPS.
Yes, the MIPS DSP ASE instructions have microMIPS encodings. They are
available on the microAptiv processors.
>
> > default:
> > MIPS_INVAL("pool32i");
> > generate_exception(ctx, EXCP_RI);
> > @@ -12196,6 +12226,18 @@ static void decode_opc (CPUMIPSState *env,
> DisasContext *ctx, int *is_branch)
> > check_insn(env, ctx, ISA_MIPS32R2);
> > /* Treat as NOP. */
> > break;
> > + case OPC_BPOSGE32: /* MIPS DSP branch */
> > + check_dsp(ctx);
> > + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> > + *is_branch = 1;
> > + break;
> > +#if defined(TARGET_MIPS64)
> > + case OPC_BPOSGE64:
> > + check_dsp(ctx);
> > + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> > + *is_branch = 1;
> > + break;
> > +#endif
>
> Same here, this can be written
>
> | case OPC_BPOSGE32: /* MIPS DSP branch */
> | #if defined(TARGET_MIPS64)
> | case OPC_BPOSGE64:
> | #endif
> | check_dsp(ctx);
> | gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> | *is_branch = 1;
> | break;
>
> > default: /* Invalid */
> > MIPS_INVAL("regimm");
> > generate_exception(ctx, EXCP_RI);
> > --
> > 1.7.9.5
> >
> >
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurel...@aurel32.net http://www.aurel32.net
-Eric
