On 10/14/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> Use stq_* for 64 bit stores.
I changed also uses of 64 bit loads to ldq. But it looks like this
makes OpenBIOS trigger alignment traps, this is the same reason why
the alignment checks aren't fully enabled. So I can't commit this yet
except for the buggy store fix.
Index: target-sparc/op_helper.c
===================================================================
--- target-sparc/op_helper.c.orig 2007-10-14 17:01:52.000000000 +0000
+++ target-sparc/op_helper.c 2007-10-14 19:48:20.000000000 +0000
@@ -170,6 +170,7 @@
void helper_ld_asi(int asi, int size, int sign)
{
uint32_t ret = 0;
+ uint64_t tmp;
#ifdef DEBUG_MXCC
uint32_t last_T0 = T0;
#endif
@@ -244,8 +245,9 @@
ret = ldl_code(T0 & ~3);
break;
case 8:
- ret = ldl_code(T0 & ~3);
- T0 = ldl_code((T0 + 4) & ~3);
+ tmp = ldq_code(T0 & ~7);
+ ret = tmp >> 32;
+ T0 = tmp & 0xffffffff;
break;
}
break;
@@ -262,8 +264,9 @@
ret = ldl_user(T0 & ~3);
break;
case 8:
- ret = ldl_user(T0 & ~3);
- T0 = ldl_user((T0 + 4) & ~3);
+ tmp = ldq_user(T0 & ~7);
+ ret = tmp >> 32;
+ T0 = tmp & 0xffffffff;
break;
}
break;
@@ -280,8 +283,9 @@
ret = ldl_kernel(T0 & ~3);
break;
case 8:
- ret = ldl_kernel(T0 & ~3);
- T0 = ldl_kernel((T0 + 4) & ~3);
+ tmp = ldq_kernel(T0 & ~7);
+ ret = tmp >> 32;
+ T0 = tmp & 0xffffffff;
break;
}
break;
@@ -303,8 +307,9 @@
ret = ldl_phys(T0 & ~3);
break;
case 8:
- ret = ldl_phys(T0 & ~3);
- T0 = ldl_phys((T0 + 4) & ~3);
+ tmp = ldq_phys(T0 & ~7);
+ ret = tmp >> 32;
+ T0 = tmp & 0xffffffff;
break;
}
break;
@@ -325,10 +330,10 @@
| ((target_phys_addr_t)(asi & 0xf) << 32));
break;
case 8:
- ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
- | ((target_phys_addr_t)(asi & 0xf) << 32));
- T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
+ tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
| ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = tmp >> 32;
+ T0 = tmp & 0xffffffff;
break;
}
break;
@@ -515,8 +520,7 @@
stl_user(T0 & ~3, T1);
break;
case 8:
- stl_user(T0 & ~3, T1);
- stl_user((T0 + 4) & ~3, T2);
+ stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
break;
}
break;
@@ -533,8 +537,7 @@
stl_kernel(T0 & ~3, T1);
break;
case 8:
- stl_kernel(T0 & ~3, T1);
- stl_kernel((T0 + 4) & ~3, T2);
+ stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
break;
}
break;
@@ -591,8 +594,7 @@
stl_phys(T0 & ~3, T1);
break;
case 8:
- stl_phys(T0 & ~3, T1);
- stl_phys((T0 + 4) & ~3, T2);
+ stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
break;
}
}
@@ -615,10 +617,8 @@
| ((target_phys_addr_t)(asi & 0xf) << 32), T1);
break;
case 8:
- stl_phys((target_phys_addr_t)(T0 & ~3)
- | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
- stl_phys((target_phys_addr_t)((T0 + 4) & ~3)
- | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ stq_phys((target_phys_addr_t)(T0 & ~7)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), ((uint64_t)T1 << 32) | T2);
break;
}
}
Index: target-sparc/op_mem.h
===================================================================
--- target-sparc/op_mem.h.orig 2007-10-14 19:41:01.000000000 +0000
+++ target-sparc/op_mem.h 2007-10-14 19:55:02.000000000 +0000
@@ -36,8 +36,7 @@
void OPPROTO glue(op_std, MEMSUFFIX)(void)
{
- glue(stl, MEMSUFFIX)(ADDR(T0), T1);
- glue(stl, MEMSUFFIX)((ADDR(T0 + 4)), T2);
+ glue(stq, MEMSUFFIX)(ADDR(T0), (T1 << 32) | (T2 & 0xffffffff));
}
void OPPROTO glue(op_ldstub, MEMSUFFIX)(void)
@@ -55,8 +54,11 @@
void OPPROTO glue(op_ldd, MEMSUFFIX)(void)
{
- T1 = glue(ldl, MEMSUFFIX)(ADDR(T0));
- T0 = glue(ldl, MEMSUFFIX)((ADDR(T0 + 4)));
+ target_ulong tmp;
+
+ tmp = glue(ldq, MEMSUFFIX)(ADDR(T0));
+ T1 = tmp >> 32;
+ T0 = tmp & 0xffffffff;
}
/*** Floating-point store ***/
