On 09/11/2012 12:11 PM, Blue Swirl wrote: > PSW_MASK_64 bit could be added to TB flags and that could be checked > during translation, then the mask needs to be applied only when the > mode is active. Whether that actually improves performance depends on > how often the bit is changed. Also all PSW writes need to be handled, > possibly causing a TB flush.
Actually I'm not sure why we check this at all, given that we only actually handle 64-bit mode -- at least as documented by the code implementing the SET ADDRESS MODE instruction. That said, we do encode the bit in TB flags, and we do perform this masking for qemu loads performed within the TB. No TB flushes are required because we simply don't match TBs with different flags. As for clst, mvst, srst, I thought about performing the masking in the TB, but didn't figure it was worth it. Do you have an opinion, Alex? r~