On 09/17/2012 03:21 PM, Peter Maydell wrote: > On 5 September 2012 20:07, Francesco Lavra <francescolavra...@gmail.com> > wrote: >> Documentation at >> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0503c/CHDEFDJF.html >> says that the entire first 512 MB can be mapped to either SMC (which is >> the default) or AXI, so if AXI is selected neither of the 2 flash banks >> is visible. Also, the same doc says that it's possible to map either >> NOR0 (default) or NOR1 to the address 0x00000000. This implies that in >> the A Series memory map VE_NORFLASH0 should be at 0x08000000 and >> VE_NORFLASH0ALIAS at 0x00000000, not the other way around (by the way, >> this is also how U-Boot defines the memory for the A5 CoreTile). Maybe >> worth a patch? > > Agreed, NORFLASH0 should be at 0x08000000 in the new memory map. Unless > anybody actually needs the aliasing of the flash at address zero, I > suggest just deleting all references to VE_NORFLASH0ALIAS.
Ok, thanks, then I'm going to send a 2 patch series, which first will fix NORFLASH0 and remove NORFLASH0ALIAS, and then will actually add the flash modelling.