On 09.10.2012, at 06:17, David Gibson wrote: > This patch adds some extra FPU state to CPUPPCState. Specifically, > fpscr is extended to a target_ulong bits, since some recent (64 bit) > CPUs now have more status bits than fit inside 32 bits. Also, we add > the 32 VSR registers present on CPUs with VSX (these extend the > standard FP regs, which together with the Altivec/VMX registers form a > 64 x 128bit register file for VSX). > > We don't actually support the instructions using these extra registers > in TCG yet, but we still need a place to store the state so we can > sync it with KVM and savevm/loadvm it. This patch updates the savevm > code to not fail on the extended state, but also does not actually > save it - that's a project for another patch. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> > --- > > v2: > * Used target_ulong instead of uint64_t, since the extended state is used > only on ppc64 targets. > * Fixed the TCG mapping of fpscr to match the new type. > --- > target-ppc/cpu.h | 4 +++- > target-ppc/machine.c | 8 ++++++-- > target-ppc/translate.c | 4 ++-- > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index faf4404..7627722 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -963,7 +963,7 @@ struct CPUPPCState { > /* floating point registers */ > float64 fpr[32]; > /* floating point status and control register */ > - uint32_t fpscr; > + target_ulong fpscr;
This will still break TCG for qemu-system-ppc64, no? Alex > > /* Next instruction pointer */ > target_ulong nip; > @@ -1014,6 +1014,8 @@ struct CPUPPCState { > /* Altivec registers */ > ppc_avr_t avr[32]; > uint32_t vscr; > + /* VSX registers */ > + uint64_t vsr[32]; > /* SPE registers */ > uint64_t spe_acc; > uint32_t spe_fscr; > diff --git a/target-ppc/machine.c b/target-ppc/machine.c > index 21ce757..5e7bc00 100644 > --- a/target-ppc/machine.c > +++ b/target-ppc/machine.c > @@ -6,6 +6,7 @@ void cpu_save(QEMUFile *f, void *opaque) > { > CPUPPCState *env = (CPUPPCState *)opaque; > unsigned int i, j; > + uint32_t fpscr; > > for (i = 0; i < 32; i++) > qemu_put_betls(f, &env->gpr[i]); > @@ -30,7 +31,8 @@ void cpu_save(QEMUFile *f, void *opaque) > u.d = env->fpr[i]; > qemu_put_be64(f, u.l); > } > - qemu_put_be32s(f, &env->fpscr); > + fpscr = env->fpscr; > + qemu_put_be32s(f, &fpscr); > qemu_put_sbe32s(f, &env->access_type); > #if defined(TARGET_PPC64) > qemu_put_betls(f, &env->asr); > @@ -90,6 +92,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) > CPUPPCState *env = (CPUPPCState *)opaque; > unsigned int i, j; > target_ulong sdr1; > + uint32_t fpscr; > > for (i = 0; i < 32; i++) > qemu_get_betls(f, &env->gpr[i]); > @@ -114,7 +117,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) > u.l = qemu_get_be64(f); > env->fpr[i] = u.d; > } > - qemu_get_be32s(f, &env->fpscr); > + qemu_get_be32s(f, &fpscr); > + env->fpscr = fpscr; > qemu_get_sbe32s(f, &env->access_type); > #if defined(TARGET_PPC64) > qemu_get_betls(f, &env->asr); > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 1042268..01c2907 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -68,7 +68,7 @@ static TCGv cpu_cfar; > #endif > static TCGv cpu_xer; > static TCGv cpu_reserve; > -static TCGv_i32 cpu_fpscr; > +static TCGv cpu_fpscr; > static TCGv_i32 cpu_access_type; > > #include "gen-icount.h" > @@ -9463,7 +9463,7 @@ void cpu_dump_state (CPUPPCState *env, FILE *f, > fprintf_function cpu_fprintf, > if ((i & (RFPL - 1)) == (RFPL - 1)) > cpu_fprintf(f, "\n"); > } > - cpu_fprintf(f, "FPSCR %08x\n", env->fpscr); > + cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); > #if !defined(CONFIG_USER_ONLY) > cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx > " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", > -- > 1.7.10.4 >