On Sun, Oct 21, 2012 at 08:48:52AM +1000, Richard Henderson wrote: > On 2012-10-21 00:48, Aurelien Jarno wrote: > > I am not sure it is the real problem, but at least the optimization of > > using the destination register as a temporary is wrong when the > > instruction might trigger an exception. In that case the result is > > written to the destination register while it should have not. > > > > This reverts commit 5793f2a47e201d251856c7956d6f7907ec0d9f1f. > > Which insn might trigger an exception? Most OP=2 insns don't. There's > divide, but that's done out-of-line, so the assignment to dst does not > happen before the exception...
Indeed there a are a few one triggering exception, but I looked too quickly and indeed they do the assignment before. There should be another problem elsewhere as reverting this patch fixes the issue. > Is this sparc64? I assume so, since I did test sparc32... > Yes it's with a sparc64 kernel. I can reproduce the problem with both a 32 and 64-bit userland, though it happens earlier with a 32-bit userland. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net
