On Fri, Oct 19, 2012 at 04:43:25PM -0400, Jason Baron wrote: > Hi, > > Qemu bits for q35 support, I'm posting the seabios changes separately. The > patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the > qemu command line. Hopefully, we can make it the default for x86 at some > future > point when we feel comfortable with it. > > The current patches have been tested with basic install testing and memory > testing > on f16, f17, windows 7 and windows 8. They can be run on the various BSD > flavors > by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches > have also been reported to work with a small dsdt change on OSX 10.6 as well. > > I've dropped the ahci migration bits, which means q35 is not migratable at the > moment. I simply haven't had time to make them more complete yet. > > I'm hoping that we'll come to some agreement on the minimal functionality > required for q35 to be merged. > > Git trees: > > git://github.com/jibaron/q35-qemu.git > git://github.com/jibaron/q35-seabios.git > > > Notes: > > I've dropped automatic load of the dsdt table on the piix for now. We can't > pull this in until we have snapshot of the dsdt aml, and I wanted it to be > done at a clean seabios freeze point (Although I guess that could be the > current snapshot). I don't see the harm in pulling this in later though. > > I've also gone to a model of the pci host being sparse: > > 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM > Controller > 00:01.0 VGA compatible controller: Cirrus Logic GD 5446 > 00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet > Controller (rev 03) > 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller > (rev 02) > 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port > SATA AHCI Controller (rev 02) > 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev > 02) > > The idea is only to populate the essential stuff at 1f, and have the rest > filled out via command line options. In this way we have minimal bus > configuration > with 1 slot occupied as in piix. Should make things easier for libvirt. And > this > way user has complete control over things. For example, I have added support > that > when '-usb' is passed the usb controllers for ich9 are filled out. > > Todo: > > -add ahci migration back (need to cover more fields, but basically works) > -add base addr for hpet in LPC device (for osx per agraf) > -convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)
- add acpi hotplug for devices behind bridge (this is needed so we can add e.g. PCI devices behind a bridge in a compliant way) > > Thanks, > > -Jason > Changes from v2: > -Patch restructure (broke out ich9 chips + data structures separately) > -added passthrough support > -add support for -usb to fill out host pci bus > -Dropped automatic load of dsdt table for piix > -cleanups > -dropped wmask on smbus (mst) > -sparse host bus > > Changes from v1: > -Updated end of low mem from 0xe0000000 -> 0xb0000000 (Gerd Hoffmann) > -so 0xb000000-0xc000000 is memconfig > -0xc000000-0xfec00000 is 32-bit pci window > -style/various cleanups > -introduced IF_AHCI > -introduced mach_if > -split dsdt out of bios, now passed for piix4 as well (Paolo, Gerd) > -Removed add opaque argument to pci_map_irq_fn (Michael S. Tsirkin) > -removed patches that were merged in v1 > > > Isaku Yamahata (6): > pci: pci capability must be in PCI space > pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt > pin swizzle > pc, pc_piix: split out pc nic initialization > pc/piix_pci: factor out smram/pam logic > pci_ids: add intel 82801BA pci-to-pci bridge id > q35: Introduce q35 pc based chipset emulator > > Jan Kiszka (5): > pci: Add class 0xc05 as 'SMBus' > q35: Suppress SMM BIOS initialization under KVM > q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic > q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and > PCI_STATUS_DETECTED_PARITY from w1cmask > q35: Add kvmclock support > > Jason Baron (15): > blockdev: Introduce a default machine blockdev interface field, > QEMUMachine->mach_if > blockdev: Introduce IF_AHCI > pc: Move ioapic_init() from pc_piix.c to pc.c > pcie: pass pcie window size to pcie_host_mmcfg_update() > pcie: Convert PCIExpressHost to use the QOM. > ich9: Add acpi support and definitions > ich9: Add the lpc chip > ich9: Add smbus > ich9: Add i82801b11 dmi-to-pci bridge > Add i21154 bridge chip. > Add a fallback bios file search, if -L fails. > q35: automatically load the q35 dsdt table > q35: add acpi-based pci hotplug. > q35: fill in usb pci slots with -usb > ich9: add support pci assignment > > blockdev.c | 17 ++- > blockdev.h | 21 ++ > hw/Makefile.objs | 1 + > hw/acpi_ich9.c | 492 +++++++++++++++++++++++++++++++++++++++++++ > hw/acpi_ich9.h | 57 +++++ > hw/boards.h | 2 +- > hw/device-hotplug.c | 2 +- > hw/highbank.c | 2 +- > hw/i21154.c | 113 ++++++++++ > hw/i21154.h | 9 + > hw/i386/Makefile.objs | 2 + > hw/i82801b11.c | 125 +++++++++++ > hw/ich9.h | 211 +++++++++++++++++++ > hw/ide.h | 6 + > hw/ide/ahci.c | 18 ++ > hw/ide/core.c | 23 ++- > hw/leon3.c | 2 +- > hw/lpc_ich9.c | 558 > +++++++++++++++++++++++++++++++++++++++++++++++++ > hw/mips_jazz.c | 4 +- > hw/pam.c | 120 +++++++++++ > hw/pam.h | 98 +++++++++ > hw/pc.c | 58 +++++ > hw/pc.h | 7 + > hw/pc_piix.c | 38 +--- > hw/pc_q35.c | 336 +++++++++++++++++++++++++++++ > hw/pc_sysfw.c | 2 +- > hw/pci.c | 25 ++- > hw/pci.h | 2 + > hw/pci_ids.h | 16 ++ > hw/pcie_host.c | 35 +++- > hw/pcie_host.h | 12 +- > hw/piix_pci.c | 65 +----- > hw/puv3.c | 2 +- > hw/q35.c | 332 +++++++++++++++++++++++++++++ > hw/q35.h | 161 ++++++++++++++ > hw/realview.c | 6 +- > hw/smbus_ich9.c | 163 ++++++++++++++ > hw/spapr.c | 2 +- > hw/sun4m.c | 24 +- > hw/versatilepb.c | 4 +- > hw/vexpress.c | 4 +- > hw/xilinx_zynq.c | 2 +- > vl.c | 56 ++++-- > 43 files changed, 3074 insertions(+), 161 deletions(-) > create mode 100644 hw/acpi_ich9.c > create mode 100644 hw/acpi_ich9.h > create mode 100644 hw/i21154.c > create mode 100644 hw/i21154.h > create mode 100644 hw/i82801b11.c > create mode 100644 hw/ich9.h > create mode 100644 hw/lpc_ich9.c > create mode 100644 hw/pam.c > create mode 100644 hw/pam.h > create mode 100644 hw/pc_q35.c > create mode 100644 hw/q35.c > create mode 100644 hw/q35.h > create mode 100644 hw/smbus_ich9.c