They are never changed once initialized, and moving them to the class
will allow to inspect them before instantiating.
Signed-off-by: Andreas Färber <afaer...@suse.de>
---
hw/sh7750.c | 10 +++++++---
target-sh4/cpu-qom.h | 6 ++++++
target-sh4/cpu.c | 18 +++++++++---------
target-sh4/cpu.h | 3 ---
4 Dateien geändert, 22 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 666f865..2259b59 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -255,6 +255,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
+ SuperHCPUClass *scc;
switch (addr) {
case SH7750_BCR1_A7:
@@ -288,11 +289,14 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr
addr)
case SH7750_CCR_A7:
return s->ccr;
case 0x1f000030: /* Processor version */
- return s->cpu->pvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->pvr;
case 0x1f000040: /* Cache version */
- return s->cpu->cvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->cvr;
case 0x1f000044: /* Processor revision */
- return s->cpu->prr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->prr;
default:
error_access("long read", addr);
abort();
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 8326ceb..b264be7 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -40,6 +40,9 @@
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @name: The name.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
*
* A SuperH CPU model.
*/
@@ -52,6 +55,9 @@ typedef struct SuperHCPUClass {
void (*parent_reset)(CPUState *cpu);
const char *name;
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
} SuperHCPUClass;
/**
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 80804ef..d4ba957 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -100,9 +100,6 @@ static void sh7750r_cpu_initfn(Object *obj)
CPUSH4State *env = &cpu->env;
env->id = SH_CPU_SH7750R;
- env->pvr = 0x00050000;
- env->prr = 0x00000100;
- env->cvr = 0x00110000;
env->features = SH_FEATURE_BCR3_AND_BCR4;
}
@@ -111,6 +108,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->name = "SH7750R";
+ scc->pvr = 0x00050000;
+ scc->prr = 0x00000100;
+ scc->cvr = 0x00110000;
}
static const TypeInfo sh7750r_type_info = {
@@ -126,9 +126,6 @@ static void sh7751r_cpu_initfn(Object *obj)
CPUSH4State *env = &cpu->env;
env->id = SH_CPU_SH7751R;
- env->pvr = 0x04050005;
- env->prr = 0x00000113;
- env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
env->features = SH_FEATURE_BCR3_AND_BCR4;
}
@@ -137,6 +134,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->name = "SH7751R";
+ scc->pvr = 0x04050005;
+ scc->prr = 0x00000113;
+ scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
}
static const TypeInfo sh7751r_type_info = {
@@ -152,9 +152,6 @@ static void sh7785_cpu_initfn(Object *obj)
CPUSH4State *env = &cpu->env;
env->id = SH_CPU_SH7785;
- env->pvr = 0x10300700;
- env->prr = 0x00000200;
- env->cvr = 0x71440211;
env->features = SH_FEATURE_SH4A;
}
@@ -163,6 +160,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->name = "SH7785";
+ scc->pvr = 0x10300700;
+ scc->prr = 0x00000200;
+ scc->cvr = 0x71440211;
}
static const TypeInfo sh7785_type_info = {
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 49dcd9e..f805778 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -179,9 +179,6 @@ typedef struct CPUSH4State {
CPU_COMMON
int id; /* CPU model */
- uint32_t pvr; /* Processor Version Register */
- uint32_t prr; /* Processor Revision Register */
- uint32_t cvr; /* Cache Version Register */
void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */
--
1.7.10.4
