Blue -- I forgot to put this patch in a target-arm pullreq, and it's my only outstanding target-arm patch for 1.4. Do you want to just apply it directly or would you prefer me to put together a single-patch pullreq?
[patchwork url: http://patchwork.ozlabs.org/patch/205269/ ] thanks -- PMM On 11 December 2012 16:11, Peter Maydell <peter.mayd...@linaro.org> wrote: > Fix a leak of a TCG temporary in code paths for VFP system register > writes for cases which UNDEF or are write-ignored. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target-arm/translate.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 3cf3604..d6fafa0 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -2737,7 +2737,6 @@ static int disas_vfp_insn(CPUARMState * env, > DisasContext *s, uint32_t insn) > } > } else { > /* arm->vfp */ > - tmp = load_reg(s, rd); > if (insn & (1 << 21)) { > rn >>= 1; > /* system register */ > @@ -2748,6 +2747,7 @@ static int disas_vfp_insn(CPUARMState * env, > DisasContext *s, uint32_t insn) > /* Writes are ignored. */ > break; > case ARM_VFP_FPSCR: > + tmp = load_reg(s, rd); > gen_helper_vfp_set_fpscr(cpu_env, tmp); > tcg_temp_free_i32(tmp); > gen_lookup_tb(s); > @@ -2757,18 +2757,21 @@ static int disas_vfp_insn(CPUARMState * env, > DisasContext *s, uint32_t insn) > return 1; > /* TODO: VFP subarchitecture support. > * For now, keep the EN bit only */ > + tmp = load_reg(s, rd); > tcg_gen_andi_i32(tmp, tmp, 1 << 30); > store_cpu_field(tmp, vfp.xregs[rn]); > gen_lookup_tb(s); > break; > case ARM_VFP_FPINST: > case ARM_VFP_FPINST2: > + tmp = load_reg(s, rd); > store_cpu_field(tmp, vfp.xregs[rn]); > break; > default: > return 1; > } > } else { > + tmp = load_reg(s, rd); > gen_vfp_msr(tmp); > gen_mov_vreg_F0(0, rn); > } > -- > 1.7.9.5 > >
