On Wed, Jan 30, 2013 at 11:05 AM, Muhammad Nouman <nouman...@gmail.com> wrote: > Hi! There is a special segment in Octeon processors (CVMSEG) > which maps a small portion of MIPS64 address space to > Data Cache. This region is used by the user applications > as scratch space and this space is saved by Octeon Kernel > on context switches. > > How can we do this mapping (i.e. some part of Mem to > DCache) in QEMU? Is there any such example code in > QEMU?
No, because QEMU does not model caches at all. In the future this could be doable with memory API, first we need to have per CPU address spaces (needed also for other reasons) in addition to the system address space. Then the cache devices could be inserted between each CPU and its address space. Then your case could be implemented by making the cache also accessible separately. But if the guest OS only uses the area as scratch space and does not play tricky games by assuming that some memory accesses to other areas result in the data appearing in the cache area or that cache flushes clear the area, it could be approximated now by simply putting some RAM into this region. > > > > Thanks >
