On Sat, Feb 2, 2013 at 5:44 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 2 February 2013 17:37, Andreas Färber <afaer...@suse.de> wrote: >> Am 02.02.2013 17:49, schrieb Peter Maydell: >>> There's nothing special about the OMAP i2c device that I know of: >>> shouldn't the test code just be using a generic "write 16 bit value >>> to memory with appropriate endianness for target CPU" function ? >> >> I asked about where to address this issue [1], no concrete answers, and >> this is the only solution I came up with. >> >> libqtest.h has no generic endian-aware memread functions unlike Alex, >> you or me expected. It reads a sequence of bytes from guest memory and >> transmits them one-by-one over the text-based qtest protocol. > > OK, so this is just busted for accessing devices. The protocol > has to have some way of letting you do a 32 bit / 16 bit / 8 bit > access (and maybe 64 bit as well while we're here). memread > and memwrite are OK for RAM accesses [ie anything you'd be > happy to have cached or buffered in a real system] but for > memory mapped registers we need to have an equivalent of > inb/inw/inl/outb/outw/outl that guarantee to do exactly one > access of exactly the required width.
I was also just making a patch (but not so nice as Andreas'). My analysis was that qtest.c and libqtest.c just pass the result of cpu_physical_memory_rw() as is, with no endian conversion. So the result needs to be converted to host CPU order just like Andreas did. I think the protocol is OK, my initial reaction was to put byte swapping there but that's not right. > > (If you want to do a workaround for 1.4 to get the test suite > running again I don't object; this is just a discussion about > what the right long term fix should be.) > > -- PMM