On Mon, 2013-02-18 at 17:37 -0500, Kevin O'Connor wrote: > The ACPI v2 spec describes a "hard" reset register. SeaBIOS could > extract it from the FADT and then use it. Of course, we'd probably > want to update the QEMU ACPI tables to implement ACPI v2 then.
This sounded great until I actually came to implement it. The PIIX reset at 0xcf9 requires *two* writes; one to set the reset type and then a second write with bit 2 set to actually do the reset. The ACPI RESET_REG definition only allows for *one* value to be written. Is that because the PIIX will actually do a hard reset when you write 0x06 to it *anyway*, despite theoretically saying that you should write 0x02 first? Or is the ACPI definition of RESET_REG simply incapable of being used on the PIIX? -- dwmw2
smime.p7s
Description: S/MIME cryptographic signature
