Ping!
Any further review on this? Id like to drop patch 8 (at it is
proof-of-concept only) and merge up to and including this. Andreas has
put RB to patches 1-6 already.
Regards,
Peter
On Mon, Feb 25, 2013 at 6:50 PM, Peter Crosthwaite
<peter.crosthwa...@xilinx.com> wrote:
> Create a separate child object to proxy the stream slave connection. This is
> setup for future work where a second stream slave connection is needed. The
> new child object is created at qdev init time and is linked back to the parent
> (the ethernet device itself) automatically.
>
> Stream slave masters differentiate which slave connection they are connected
> to
> by linking to the proxy object rather than the parent.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> change from v1:
> renamed data-stream proxy link to "axistream-connected-target"
> rebased ontop of realize conversion
> reworked error return mechanism (Andreas review)
> inlined child device state struct into parents (Andreas review)
> replaced object_new() -> object_initialize() (Andreas review)
>
> hw/petalogix_ml605_mmu.c | 6 ++++-
> hw/xilinx_axienet.c | 60 ++++++++++++++++++++++++++++++++++++++++++---
> 2 files changed, 61 insertions(+), 5 deletions(-)
>
> diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
> index e3528c0..4223173 100644
> --- a/hw/petalogix_ml605_mmu.c
> +++ b/hw/petalogix_ml605_mmu.c
> @@ -79,6 +79,7 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
> const char *cpu_model = args->cpu_model;
> MemoryRegion *address_space_mem = get_system_memory();
> DeviceState *dev, *dma, *eth0;
> + Object *peer;
> MicroBlazeCPU *cpu;
> SysBusDevice *busdev;
> CPUMBState *env;
> @@ -142,7 +143,10 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
> xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(dma),
> 0x82780000, irq[3], 0x1000, 0x1000);
>
> - xilinx_axidma_init(dma, STREAM_SLAVE(eth0), 0x84600000, irq[1], irq[0],
> + peer = object_property_get_link(OBJECT(eth0), "data-stream", NULL);
> + assert(peer);
> +
> + xilinx_axidma_init(dma, STREAM_SLAVE(peer), 0x84600000, irq[1], irq[0],
> 100 * 1000000);
>
> {
> diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
> index 27d94bd..a4ec1d8 100644
> --- a/hw/xilinx_axienet.c
> +++ b/hw/xilinx_axienet.c
> @@ -32,10 +32,15 @@
> #define DPHY(x)
>
> #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
> +#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
>
> #define XILINX_AXI_ENET(obj) \
> OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
>
> +#define XILINX_AXI_ENET_DATA_STREAM(obj) \
> + OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> + TYPE_XILINX_AXI_ENET_DATA_STREAM)
> +
> /* Advertisement control register. */
> #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
> #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
> @@ -310,13 +315,21 @@ struct TEMAC {
> void *parent;
> };
>
> +typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
> typedef struct XilinxAXIEnet XilinxAXIEnet;
>
> +struct XilinxAXIEnetStreamSlave {
> + Object parent;
> +
> + struct XilinxAXIEnet *enet;
> +} ;
> +
> struct XilinxAXIEnet {
> SysBusDevice busdev;
> MemoryRegion iomem;
> qemu_irq irq;
> StreamSlave *tx_dev;
> + XilinxAXIEnetStreamSlave rx_data_dev;
> NICState *nic;
> NICConf conf;
>
> @@ -800,9 +813,11 @@ static void eth_cleanup(NetClientState *nc)
> }
>
> static void
> -axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t
> *hdr)
> +axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
> + uint32_t *hdr)
> {
> - XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
> + XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> + XilinxAXIEnet *s = ds->enet;
>
> /* TX enable ? */
> if (!(s->tc & TC_TX)) {
> @@ -853,6 +868,18 @@ static NetClientInfo net_xilinx_enet_info = {
> static void xilinx_enet_realize(DeviceState *dev, Error **errp)
> {
> XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
> + XilinxAXIEnetStreamSlave *ds =
> XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> + Error *local_errp = NULL;
> +
> + object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
> + (Object **) &ds->enet, &local_errp);
> + if (local_errp) {
> + goto xilinx_enet_realize_fail;
> + }
> + object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_errp);
> + if (local_errp) {
> + goto xilinx_enet_realize_fail;
> + }
>
> qemu_macaddr_default_if_unset(&s->conf.macaddr);
> s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
> @@ -865,6 +892,12 @@ static void xilinx_enet_realize(DeviceState *dev, Error
> **errp)
> s->TEMAC.parent = s;
>
> s->rxmem = g_malloc(s->c_rxmem);
> + return;
> +
> +xilinx_enet_realize_fail:
> + if (!*errp) {
> + *errp = local_errp;
> + }
> }
>
> static void xilinx_enet_init(Object *obj)
> @@ -877,6 +910,11 @@ static void xilinx_enet_init(Object *obj)
> (Object **) &s->tx_dev, &errp);
> assert_no_error(errp);
>
> + object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM);
> + object_property_add_child(OBJECT(s), "axistream-connected-target",
> + (Object *)&s->rx_data_dev, &errp);
> + assert_no_error(errp);
> +
> sysbus_init_irq(sbd, &s->irq);
>
> memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
> @@ -894,12 +932,17 @@ static Property xilinx_enet_properties[] = {
> static void xilinx_enet_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
>
> dc->realize = xilinx_enet_realize;
> dc->props = xilinx_enet_properties;
> dc->reset = xilinx_axienet_reset;
> - ssc->push = axienet_stream_push;
> +}
> +
> +static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
> +{
> + StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> +
> + ssc->push = data;
> }
>
> static const TypeInfo xilinx_enet_info = {
> @@ -908,6 +951,14 @@ static const TypeInfo xilinx_enet_info = {
> .instance_size = sizeof(XilinxAXIEnet),
> .class_init = xilinx_enet_class_init,
> .instance_init = xilinx_enet_init,
> +};
> +
> +static const TypeInfo xilinx_enet_data_stream_info = {
> + .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
> + .parent = TYPE_OBJECT,
> + .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> + .class_init = xilinx_enet_stream_class_init,
> + .class_data = axienet_data_stream_push,
> .interfaces = (InterfaceInfo[]) {
> { TYPE_STREAM_SLAVE },
> { }
> @@ -917,6 +968,7 @@ static const TypeInfo xilinx_enet_info = {
> static void xilinx_enet_register_types(void)
> {
> type_register_static(&xilinx_enet_info);
> + type_register_static(&xilinx_enet_data_stream_info);
> }
>
> type_init(xilinx_enet_register_types)
> --
> 1.7.0.4
>
