By default these interrupts are clear on read. Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com> ---
hw/xilinx_spips.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c index 734adf0..261d948 100644 --- a/hw/xilinx_spips.c +++ b/hw/xilinx_spips.c @@ -330,6 +330,10 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, mask = 0x0002FFFF; break; case R_INTR_STATUS: + ret = s->regs[addr] & IXR_ALL; + s->regs[addr] = 0; + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + return ret; case R_INTR_MASK: mask = IXR_ALL; break; -- 1.7.0.4