On Wed, Apr 03, 2013 at 02:04:09PM +1000, Peter Crosthwaite wrote:
> When the conditions blocking receiving are cleared, check for buffered rx
> packets.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Acked-by: Edgar E. Iglesias <edgar.igles...@gmail.com>
> ---
> hw/xilinx_axienet.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
> index 5785290..07c4bad 100644
> --- a/hw/xilinx_axienet.c
> +++ b/hw/xilinx_axienet.c
> @@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr,
> s->rcw[addr & 1] = value;
> if ((addr & 1) && value & RCW1_RST) {
> axienet_rx_reset(s);
> + } else {
> + qemu_flush_queued_packets(qemu_get_queue(s->nic));
> }
> break;
>
> --
> 1.7.0.4
>
