From: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.
Cc: Wendy Liang <jli...@xilinx.com>
Cc: Jason Wu <hua...@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reported-by: Jason Wu <hua...@xilinx.com>
Message-id:
494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/cadence_uart.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index 5426f10..421ec99 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -157,6 +157,7 @@ static void uart_rx_reset(UartState *s)
{
s->rx_wpos = 0;
s->rx_count = 0;
+ qemu_chr_accept_input(s->chr);
s->r[R_SR] |= UART_SR_INTR_REMPTY;
s->r[R_SR] &= ~UART_SR_INTR_RFUL;
--
1.7.9.5
