On Wed, May 08, 2013 at 04:48:22PM +0200, Torbjorn Granlund wrote: > Aurelien Jarno <aurel...@aurel32.net> writes: > > That said this does implement neither the specification nor the silicon > behaviour. This is fine for 1.5 as we are in freeze period, but this > should be fixed for the 1.6 release. > > I talked to IBM now. Reserved fields should be ignored by hardware.
As it seems you have good contact with IBM, could you please ask them to fix their manuals? > The architecture owner is IBM, not Freescale. That Freescale deviates > from the architecture, is something that you may decide to ignore, > unless it is vital for qemu's behaviour in practice. At least Freescale CPUs matches what IBM documentation says. IBM CPUs doesn't. > I very much doubt that L = 1 often, for code targeting a 32-bit > processor. > > Trying to mimic decoding flaws on a per-processor basis, is going to > take a lot of research, and will be prone to errors. > > So as far as I can tell, the patch is correct as per the architecture > specification. No it's not correct, it doesn't match neither Freescale nor IBM behaviour. It also means the same code executed on a 32-bit emulated CPU run with qemu-system-ppc will behave differently than when run with qemu-system-ppc64. This is fine for now as we are in freeze period, but should be fixed afterwards. > One caveat though: Does 32-bit implementations define the SF bit, or > else, does qemu define it and make sure it is 0 for 32-bit emulation? > If not, the patch might cause trouble. QEMU makes sure it is 0 for 32-bit CPU. > Congrats, you read a "user message" until the last line. :-) > Like I did for the previous one. Would be nice if you can do the same. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net
