On Tue, Nov 17, 2009 at 12:35 AM, Jamie Lokier <ja...@shareable.org> wrote: > Artyom Tarasenko wrote: >> I don't know, how the real sun4m reacts in the case where irq stays >> on, not being cleared. >> It can not be though that it would try to process irq for every next >> tick. The CPU must have some time to clear the pending irq, so it must >> be edge triggered too, at least in a way. > > In general, most CPUs have a "disable interrupts" flag which is set at > the same time as calling the irq handler. > > That's enough, even if everything about interrupts is level triggered, > so you can't assume anything is edge triggered just from that alone. > > However if a CPU doesn't have an "disable interrupts" flag, then of > course the triggering must be edge triggered somewhere.
Sparc has a flag for disabling all traps. Also the minimum allowed interrupt level (PIL) can be selected from 0 to 14, level 15 is non-maskable from CPU point of view. This level allows interrupt handlers to be interrupted by a higher priority interrupt, if the traps are enabled.
