On 5 August 2013 12:48, Anup Patel <a...@brainfault.org> wrote:
>> +static const MemMapEntry a15memmap[] = {
>> + [VIRT_FLASH] = { 0, 0x100000 },
>
> IMHO, 1 MB of flash is small for possible future expansion. If mach-virt
> becomes popular then we can expect people running UBoot or UEFI or
> .... from this flash.
>
> I think having 16 MB of flash would be good because it is multiple of
> 2 MB hence we can also create section entries for it in Stage2 TTBL.
Seems reasonable.
>> + [VIRT_CPUPERIPHS] = { 0x100000, 0x8000 },
>
> I would suggest to start peripheral space at 2 MB boundary and also
> have its total size in multiple of 2 MB.
The total size here is fixed by the CPU hardware -- an A15's
private peripheral space is only 0x8000 in size.
> This will enable us to create 2 MB
> entries in Stage2 TTBL for trapping which in-turn can help in performance
> by reducing Stage2 TTBL walks.
>
> I am sure there won't be too many peripherals in mach-virt so, it would
> even better if we can have base address of each peripheral to be at
> 2 MB boundary.
Why does each individual peripheral have to be at a 2MB boundary?
I would expect the kernel to just have a single "nothing mapped"
here stage 2 table entry (or entries) covering the whole of the
mmio peripheral region regardless of how many devices happen
to be inside it.
thanks
-- PMM
