On Thu, 2013-09-05 at 14:59 +0200, Alexander Graf wrote: > > The embedded PPCs have simply a per-page E bit in the TLB > controlling > > the endianness of accesses through the translation, the endianness > is > > "clean" in that case, and the bus doesn't flip around so it's akin > to > > what P7 does but with a finer granularity. > > So on P7 basically everything that goes from registers out is > byte-swapped, including any RAM access and MMIOs? I think that's > basically what the current little endian mode implements (though it > might miss a few places, like FPU or Altivec, but I'd consider that > bugs).
Yes. There are some oddities with VSX though (it does PDP endian iirc). Cheers, Ben.