2013/6/30 Alexander Graf <ag...@suse.de>: > The L2CR register contains a number of bits that either impose configuration > which we can't deal with or mean "something is in progress until the bit is > 0 again". > > Since we don't model the former and we do want to accomodate guests using the > latter semantics, let's just ignore writes to L2CR. That way guests always > read > back 0 and are usually happy with that.
Hi, It does not seem to simply ignore writes to L2CR. The kernel we run on qemu no longer works without deleting the write instructions to L2CR. And a simple test of executing a write to L2CR seems to generate an exception instead of ignoring it : > $ qemu-system-ppc -cpu e600 -M prep -m 256M -bios prep_bios.elf -d in_asm > Trying to write invalid spr 1017 (0x3f9) at fffffffc > Trying to write invalid spr 1017 (0x3f9) at fffffffc > IN: > 0xfffffffc: mtl2cr r0 > > invalid/unsupported opcode: 00 - 00 - 00 (00000000) fff00700 0 > IN: > 0xfff00700: .long 0x0 Is it really what you wanted ? -- Julio Guerra
