On Mon, 2013-09-09 at 14:16 +0100, Peter Maydell wrote: > On 9 September 2013 14:07, Marcel Apfelbaum <marce...@redhat.com> wrote: > > This is exactly my point. ALL device on the bus can be masters > > of a DMA transaction. So adding an interface as suggested by > > Michael: pci_set_master_for_master_abort(PCIBus *, PCIDevice *) > > for the general case (a device doing DMA) it is too far from reality. > > Actually I don't think it would be too painful. > At the moment in do_pci_register_device() we do this to > create the memory region used by a device for its bus > master transactions: > > memory_region_init_alias(&pci_dev->bus_master_enable_region, > OBJECT(pci_dev), "bus master", > dma_as->root, 0, > memory_region_size(dma_as->root)); > > If instead of using this alias directly as the > bus_master_enable region you instead: > * create a container region > * create a 'background' region at negative priority > (ie one per device, and you can make the 'opaque' pointer > point to the device, not the bus) > * put the alias and the background region into the container > * use the container as the bus_master_enable region > > then you will get in your callback a pointer to the > device which caused the abort. You can then have your > callback call a method defined on PCIDevice which we > implement: > * as do-nothing in the PCI device base class > * as set-the-master-abort bit in the PCI host bridge > class The Received Master Abort bit must be set for the initiator. In the case described here this bit mast be set in the device register rather that in host bridge.
> (and anybody who wants to get fancy about handling aborts > can override it in their own device implementation) > > That seems achievable without really requiring new > infrastructure. Have I missed something that wouldn't > work if we did this? The idea seems correct (and cool!) to me (I'll look deeper), but it covers only one way: upstream. We need to unify this with the downstream: The cpu accesses to unassigned memory should result in the callback to the host bridge. All we need is that all the host bridges to have a common class and following the same idea we get the downstream (The host bridge inititates all transactions on the bus on behalf of the cpu) If this works, we don't need no work around! Marcel > > thanks > -- PMM
