Signed-off-by: Richard Henderson <r...@twiddle.net> --- tcg/aarch64/tcg-target.c | 12 ++++++++++++ tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bc1ca84..b7f7fa5 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -300,6 +300,8 @@ typedef enum { INSN_LSRV = 0x1ac02400, INSN_ASRV = 0x1ac02800, INSN_RORV = 0x1ac02c00, + INSN_SMULH = 0x9b407c00, + INSN_UMULH = 0x9bc07c00, /* Bitfield instructions */ INSN_BFM = 0x33000000, @@ -1597,6 +1599,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[5], const_args[4], const_args[5], c2); break; + case INDEX_op_muluh_i64: + tcg_fmt_Rdnm(s, INSN_UMULH, 1, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_fmt_Rdnm(s, INSN_SMULH, 1, a0, a1, a2); + break; + case INDEX_op_mov_i64: case INDEX_op_mov_i32: case INDEX_op_movi_i64: @@ -1724,6 +1733,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } }, { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, + { INDEX_op_muluh_i64, { "r", "r", "r" } }, + { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f311954..52c6c23 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -89,8 +89,8 @@ typedef enum { #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 enum { TCG_AREG0 = TCG_REG_X19, -- 1.8.3.1