On Wed, Sep 18, 2013 at 09:40:19AM +0200, Paolo Bonzini wrote: > Il 18/09/2013 07:48, Michael S. Tsirkin ha scritto: > > So I think the fix is actually obeying ordering rules, > > that is know that write is in progress > > and flush on read. > > I think this can be modeled as a generic, synchronous > (*busmaster_cancel)(PCIDevice*) callback, that is called after bus > master is turned off. You don't even really have to wait for a read.
Not really. Bus master is just an single instance of the bigger issue. It could be any device-specific register just as well. PCI reads and writes must obey ordering rules. ATM MMIO and DMA achieve this by using a single lock. If you want to move MMIO and DMA out of a common lock you must find some other way to force ordering. > > I think moving memory region destroy out to finalize makes sense > > irrespectively, as long as destroy is made idempotent so we can simply > > destroy everything without worrying whether we initialized it. > > > > The rest of the changes will be harder, we'll have to do > > them carefully on a case by case basis. > > Good, we are in agreement then. > > Paolo