On 09/26/2013 05:48 PM, Alexander Graf wrote: > + switch (size) { > + case 0: > + idx = get_bits(imm5, 1, 4) << 0; > + tcg_gen_ld8u_i64(cpu_reg(rd), cpu_env, freg_offs_n + idx); > + break; > + case 1: > + idx = get_bits(imm5, 2, 3) << 1; > + tcg_gen_ld16u_i64(cpu_reg(rd), cpu_env, freg_offs_n + idx); > + break; > + case 2: > + idx = get_bits(imm5, 3, 2) << 2; > + tcg_gen_ld32u_i64(cpu_reg(rd), cpu_env, freg_offs_n + idx); > + break; > + case 3: > + idx = get_bits(imm5, 4, 1) << 3; > + tcg_gen_ld_i64(cpu_reg(rd), cpu_env, freg_offs_n + idx); > + break; > + }
I see no offset adjustment for big-endian host here. r~