On Wed, 2 Dec 2009, Alexander Graf wrote: > > On 01.12.2009, at 19:33, Dima Ilyevsky wrote: > > > Hello All, > > > > I have a question about read permissions of TBL SPR for all ppc processors: > > I have discovered that my application, compiled by WindRiver diab compiler > > and running in vxworks OS on ppc405 architecture bumps into exception > > generated when trying to read TBL or TBU registers: > > Unless Linux does something funky, mftlb, mftbu (and mftb on 64 bit) are > readable from PR=1. > > int main() > { > long tbu=0, tbl=0; > > asm("mftbu %0" : "=r" (tbu)); > asm("mftbl %0" : "=r" (tbl)); > > printf("TB: %#x %#x\n", tbl, tbu); > } > > ag...@lychee:/tmp> ./mftb > TB: 0xc0397180 0x603 > > However it can't be written to: > > asm("mttbl %0" : : "r" (tbl)); > > ag...@lychee:/tmp> ./mftb > Illegal instruction
7.2.1 Writing the Time Base Writing the Time Base is privileged, and can be done only in hypervisor state. Reading the Time Base is not privileged; it is discussed in Chapter 4 of Book II. > > > So yes, I'd suspect a bug in qemu here. Feel free to send a patch. > > Alex > -- mailto:av1...@comtv.ru