Paolo Bonzini <pbonz...@redhat.com> writes: > Il 10/10/2013 18:01, Paolo Bonzini ha scritto: >> Il 10/10/2013 16:42, arm...@redhat.com ha scritto: >>> From: Markus Armbruster <arm...@redhat.com> >>> >>> An ICH9 southbridge contains several PCI devices, some of them with >>> multiple functions. We model each function as a separate qdev. Two >>> of them need some special wiring set up in pc_q35_init() to work: the >>> LPC controller at 00:1f.0, and the SMBus controller at 00:1f.3. >>> >>> Signed-off-by: Markus Armbruster <arm...@redhat.com> >>> --- >>> hw/i2c/smbus_ich9.c | 6 +++++- >>> hw/isa/lpc_ich9.c | 7 +++++-- >>> 2 files changed, 10 insertions(+), 3 deletions(-) >>> >>> diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c >>> index c1ffa34..8d47eaf 100644 >>> --- a/hw/i2c/smbus_ich9.c >>> +++ b/hw/i2c/smbus_ich9.c >>> @@ -97,11 +97,15 @@ static void ich9_smb_class_init(ObjectClass *klass, >>> void *data) >>> k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6; >>> k->revision = ICH9_A2_SMB_REVISION; >>> k->class_id = PCI_CLASS_SERIAL_SMBUS; >>> - dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain >>> why */ >>> dc->vmsd = &vmstate_ich9_smbus; >>> dc->desc = "ICH9 SMBUS Bridge"; >>> k->init = ich9_smbus_initfn; >>> k->config_write = ich9_smbus_write_config; >>> + /* >>> + * Reason: part of ICH9 southbridge, needs to be wired up by >>> + * pc_q35_init() >>> + */ >>> + dc->cannot_instantiate_with_device_add_yet = true; >>> } >>> >>> i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base) >>> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c >>> index ad841b5..d00d698 100644 >>> --- a/hw/isa/lpc_ich9.c >>> +++ b/hw/isa/lpc_ich9.c >>> @@ -604,14 +604,17 @@ static void ich9_lpc_class_init(ObjectClass *klass, >>> void *data) >>> dc->reset = ich9_lpc_reset; >>> k->init = ich9_lpc_initfn; >>> dc->vmsd = &vmstate_ich9_lpc; >>> - dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain >>> why */ >>> k->config_write = ich9_lpc_config_write; >>> dc->desc = "ICH9 LPC bridge"; >>> k->vendor_id = PCI_VENDOR_ID_INTEL; >>> k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; >>> k->revision = ICH9_A2_LPC_REVISION; >>> k->class_id = PCI_CLASS_BRIDGE_ISA; >>> - >>> + /* >>> + * Reason: part of ICH9 southbridge, needs to be wired up by >>> + * pc_q35_init() >>> + */ >>> + dc->cannot_instantiate_with_device_add_yet = true; >>> } >>> >>> static const TypeInfo ich9_lpc_info = { >>> >> >> I think SMBus is fine. Even though the standard configuration of the >> Q35 SMBus cannot be reproduced with -device, that's a problem of >> hw/i2c/smbus_eeprom.c, not of the smbus bridge itself. I think >> hw/i2c/smbus_eeprom.c should rather be marked as >> cannot_instantiate_with_device_add_yet (which makes sense, because it >> has a PROP_PTR). >> >> Alternatively, you can resuscitate the first two patches of >> http://lists.gnu.org/archive/html/qemu-devel/2012-02/msg00449.html
Getting rid of pointer properties is useful work, but outside the scope of this series. > Ah, got it---the SMBus and LPC need to be connected to each other. Yup, that's the reason. > Still, the SMBus EEPROM is a candidate for > cannot_instantiate_with_device_add_yet. I'll add it in the next version, along with all other devices with pointer properties. Thanks!