This patch adds the VSX floating point add instructions that are defined by V2.06 of the PowerPC ISA: xsadddp, xvadddp and xvaddsp.
Signed-off-by: Tom Musta <tommu...@gmail.com> --- target-ppc/fpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target-ppc/helper.h | 6 ++++++ target-ppc/translate.c | 12 ++++++++++++ 3 files changed, 64 insertions(+), 0 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index cea94ac..8cbc905 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1758,3 +1758,49 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) } #define float64_to_float64(x, env) x + +/* VSX_ADD - VSX floating point add + * op - instruction mnemonic + * nels - number of elements (1, 2 or 4) + * tp - type (float32 or float64) + * fld - vsr_t field (f32 or f64) + * sfprf - set FPRF + */ +#define VSX_ADD(op, nels, tp, fld, sfprf) \ +void helper_##op(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xt, xa, xb; \ + int i; \ + \ + getVSR(xA(opcode), &xa, env); \ + getVSR(xB(opcode), &xb, env); \ + getVSR(xT(opcode), &xt, env); \ + helper_reset_fpstatus(env); \ + \ + for (i = 0; i < nels; i++) { \ + if (unlikely(tp##_is_infinity(xa.fld[i]) && \ + tp##_is_infinity(xb.fld[i]) && \ + tp##_is_neg(xa.fld[i]) != tp##_is_neg(xb.fld[i]))) { \ + xt.fld[i] = float64_to_##tp( \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, \ + sfprf), \ + &env->fp_status); \ + } else { \ + if (unlikely(tp##_is_signaling_nan(xa.fld[i]) || \ + tp##_is_signaling_nan(xb.fld[i]))) { \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + } \ + xt.fld[i] = tp##_add(xa.fld[i], xb.fld[i], &env->fp_status); \ + if (sfprf) { \ + helper_compute_fprf(env, xt.fld[i], sfprf); \ + } \ + } \ + } \ + \ + putVSR(xT(opcode), &xt, env); \ + helper_float_check_status(env); \ +} + +VSX_ADD(xsadddp, 1, float64, f64, 1) +VSX_ADD(xvadddp, 2, float64, f64, 0) +VSX_ADD(xvaddsp, 4, float32, f32, 0) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 56814b5..30e6aa4 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -251,6 +251,12 @@ DEF_HELPER_4(vcfsx, void, env, avr, avr, i32) DEF_HELPER_4(vctuxs, void, env, avr, avr, i32) DEF_HELPER_4(vctsxs, void, env, avr, avr, i32) +DEF_HELPER_2(xsadddp, void, env, i32) + +DEF_HELPER_2(xvadddp, void, env, i32) + +DEF_HELPER_2(xvaddsp, void, env, i32) + DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) DEF_HELPER_2(efscfuf, i32, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5b51c0c..7aa17e1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7293,6 +7293,12 @@ static void gen_##name(DisasContext * ctx) \ tcg_temp_free_i32(opc); \ } +GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) + +GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) + +GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) + #define VSX_LOGICAL(name, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ @@ -9975,6 +9981,12 @@ GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), +GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), + +GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), + +GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), + #undef VSX_LOGICAL #define VSX_LOGICAL(name, opc2, opc3, fl2) \ GEN_XX3FORM(name, opc2, opc3, fl2) -- 1.7.1