On Mon, Nov 25, 2013 at 5:41 PM, liguang <lig.f...@cn.fujitsu.com> wrote:
> Signed-off-by: liguang <lig.f...@cn.fujitsu.com>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/sunxi-soc.c | 113
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 114 insertions(+), 0 deletions(-)
> create mode 100644 hw/arm/sunxi-soc.c
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 3671b42..f9f3071 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
>
> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> obj-y += omap1.o omap2.o strongarm.o
> +obj-y += sunxi-soc.o
> diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
> new file mode 100644
> index 0000000..857b0ab
> --- /dev/null
> +++ b/hw/arm/sunxi-soc.c
> @@ -0,0 +1,113 @@
> +/*
> + * Allwinner sunxi series SoC emulation
> + *
> + * Copyright (C) 2013 Li Guang
> + * Written by Li Guang <lig.f...@cn.fujitsu.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "hw/sysbus.h"
> +#include "hw/devices.h"
> +#include "hw/boards.h"
> +#include "hw/arm/arm.h"
> +#include "hw/ptimer.h"
> +#include "hw/char/serial.h"
> +#include "hw/timer/sunxi-pit.h"
> +#include "hw/intc/sunxi-pic.h"
> +
> +#include "sysemu/sysemu.h"
> +#include "exec/address-spaces.h"
> +
> +
> +#define SUNXI_PIC_REG_BASE 0x01c20400
> +#define SUNXI_PIT_REG_BASE 0x01c20c00
> +#define SUNXI_UART0_REG_BASE 0x01c28000
> +
> +static struct arm_boot_info sunxi_binfo = {
> + .loader_start = 0x40000000,
> + .board_id = 0x1008,
> +};
> +
> +static void sunxi_init(QEMUMachineInitArgs *args)
> +{
> + ram_addr_t ram_size = args->ram_size;
> + const char *cpu_model = args->cpu_model;
> + const char *kernel_filename = args->kernel_filename;
> + const char *kernel_cmdline = args->kernel_cmdline;
> + ARMCPU *cpu;
> + MemoryRegion *address_space_mem = get_system_memory();
> + MemoryRegion *ram = g_new(MemoryRegion, 1);
> + MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
> + qemu_irq pic[95];
> + DeviceState *dev;
> + uint8_t i;
> +
> + /*here we currently support sunxi-4i*/
> + cpu_model = "cortex-a8";
> + cpu = cpu_arm_init(cpu_model);
> + if (!cpu) {
> + fprintf(stderr, "Unable to find CPU definition\n");
> + exit(1);
> + }
> +
> + memory_region_init_ram(ram, NULL, "sunxi-soc.ram", ram_size);
> + memory_region_add_subregion(address_space_mem, 0, ram);
> + memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
> + memory_region_add_subregion(address_space_mem, 0x40000000, ram_alias);
> +
> + dev = sysbus_create_varargs(TYPE_SUNXI_PIC, SUNXI_PIC_REG_BASE,
> + qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
> + qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
> + NULL);
> + for (i = 0; i < 95; i++) {
> + pic[i] = qdev_get_gpio_in(dev, i);
> + }
> +
> + sysbus_create_varargs(TYPE_SUNXI_PIT, SUNXI_PIT_REG_BASE, pic[22],
> pic[23],
> + pic[24], pic[25], pic[67], pic[68], NULL);
> +
> + serial_mm_init(address_space_mem, SUNXI_UART0_REG_BASE, 2, pic[1],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> +/*
> + serial_mm_init(address_space_mem, SUNXI_UART1_REG_BASE, 2, pic[2],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART2_REG_BASE, 2, pic[3],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART3_REG_BASE, 2, pic[4],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART4_REG_BASE, 2, pic[17],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART5_REG_BASE, 2, pic[18],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART6_REG_BASE, 2, pic[19],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> + serial_mm_init(address_space_mem, SUNXI_UART7_REG_BASE, 2, pic[20],
> 115200,
> + serial_hds[0], DEVICE_NATIVE_ENDIAN);
> +*/
Why the commented out serial ports?
Regards,
Peter
> + sunxi_binfo.ram_size = ram_size;
> + sunxi_binfo.kernel_filename = kernel_filename;
> + sunxi_binfo.kernel_cmdline = kernel_cmdline;
> + arm_load_kernel(cpu, &sunxi_binfo);
> +}
> +
> +static QEMUMachine sunxi_machine = {
> + .name = "sunxi",
> + .desc = "Allwinner's SoC (sunxi series)",
> + .init = sunxi_init,
> +};
> +
> +static void sunxi_machine_init(void)
> +{
> + qemu_register_machine(&sunxi_machine);
> +}
> +
> +machine_init(sunxi_machine_init);
> --
> 1.7.2.5
>
>
