On 12/07/2013 02:19 AM, Peter Maydell wrote: > From: Alexander Graf <ag...@suse.de> > > Add support for the instructions described in "C3.5.10 Logical > (shifted register)". > > We store the flags in the same locations as the 32 bit decoder. > This is slightly awkward when calculating 64 bit results, but seems > a better tradeoff than having to rework the whole 32 bit decoder > and also make 32 bit result calculation in A64 awkward. > > Signed-off-by: Alexander Graf <ag...@suse.de> > [claudio: some refactoring to avoid hidden allocation of temps, > rework flags, use enums for shift types, > renaming of functions] > Signed-off-by: Claudio Fontana <claudio.font...@linaro.org> > [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target-arm/translate-a64.c | 197 > ++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 191 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <r...@twiddle.net> r~
