Kronecker may have said that "God made the integers, all the rest is the work of man"; however he did not suggest who we should blame for float-to-integer conversions. Those turn out to be sufficiently tricky that they're going to get a patchset all of their own. In the meantime this is most of the rest of the A64 floating point support. (Some other 1-src FP instructions like sqrt will also be deferred to the next patchset.)
This patchset sits on top of the previous one (now almost entirely codereviewed); you can find a git tree at git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-fifth-set web UI: https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-fifth-set thanks -- PMM Alexander Graf (5): target-arm: A64: Add support for dumping AArch64 VFP register state target-arm: A64: Add "Floating-point data-processing (2 source)" insns target-arm: A64: Add "Floating-point data-processing (3 source)" insns target-arm: A64: Add fmov (scalar, immediate) instruction target-arm: Give the FPSCR rounding modes names Claudio Fontana (3): target-arm: A64: Add support for floating point compare target-arm: A64: Add support for floating point conditional compare target-arm: A64: Add support for floating point cond select Peter Maydell (2): target-arm: A64: Fix vector register access on bigendian hosts target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum target-arm/cpu.h | 9 + target-arm/helper-a64.c | 45 ++++ target-arm/helper-a64.h | 4 + target-arm/helper.c | 37 +--- target-arm/helper.h | 15 +- target-arm/neon_helper.c | 12 - target-arm/translate-a64.c | 532 ++++++++++++++++++++++++++++++++++++++++++--- target-arm/translate.c | 16 +- 8 files changed, 585 insertions(+), 85 deletions(-) -- 1.8.5
