On Wed, Jan 8, 2014 at 2:19 PM, Roy Franz <roy.fr...@linaro.org> wrote:
> The 9118 ethernet controller supports transmission of multi-buffer packets
> with arbitrary byte alignment of the start and end bytes. All writes to
> the packet fifo are 32 bits, so the controller discards bytes at the beginning
> and end of each buffer based on the 'Data start offset' and 'Buffer size'
> of the TX command 'A' format.
>
> This patch uses the provided buffer length to limit the bytes transmitted.
> Previously all the bytes of the last 32-bit word written to the TX fifo
> were added to the internal transmit buffer structure resulting in more bytes
> being transmitted than were submitted to the hardware in the command. This
> resulted in extra bytes being inserted into the middle of multi-buffer
> packets when the non-final buffers had non-32bit aligned ending addresses.
>
> Signed-off-by: Roy Franz <roy.fr...@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> hw/net/lan9118.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
> index bb0c503..e528290 100644
> --- a/hw/net/lan9118.c
> +++ b/hw/net/lan9118.c
> @@ -763,7 +763,7 @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
> if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
> s->txp->pad--;
> } else {
> - n = 4;
> + n = MIN(4, s->txp->buffer_size + s->txp->offset);
> while (s->txp->offset) {
> val >>= 8;
> n--;
> --
> 1.7.10.4
>
>
