Add support for the AArch32 Advanced SIMD VRINTZ instruction.
Signed-off-by: Will Newton <will.new...@linaro.org>
---
target-arm/translate.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b6d11db..16242d3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4710,6 +4710,7 @@ static const uint8_t neon_3r_sizes[] = {
#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
#define NEON_2RM_VSHLL 38
#define NEON_2RM_VRINTX 41
+#define NEON_2RM_VRINTZ 43
#define NEON_2RM_VCVT_F16_F32 44
#define NEON_2RM_VCVT_F32_F16 46
#define NEON_2RM_VRECPE 56
@@ -4725,7 +4726,8 @@ static int neon_2rm_is_float_op(int op)
{
/* Return true if this neon 2reg-misc op is float-to-float */
return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
- op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F);
+ op == NEON_2RM_VRINTX || op == NEON_2RM_VRINTZ ||
+ op >= NEON_2RM_VRECPE_F);
}
/* Each entry in this array has bit n set if the insn allows
@@ -4770,6 +4772,7 @@ static const uint8_t neon_2rm_sizes[] = {
[NEON_2RM_VQMOVN] = 0x7,
[NEON_2RM_VSHLL] = 0x7,
[NEON_2RM_VRINTX] = 0x4,
+ [NEON_2RM_VRINTZ] = 0x4,
[NEON_2RM_VCVT_F16_F32] = 0x2,
[NEON_2RM_VCVT_F32_F16] = 0x2,
[NEON_2RM_VRECPE] = 0x4,
@@ -6489,6 +6492,20 @@ static int disas_neon_data_insn(CPUARMState * env,
DisasContext *s, uint32_t ins
tcg_temp_free_ptr(fpstatus);
break;
}
+ case NEON_2RM_VRINTZ:
+ {
+ TCGv_i32 tcg_rmode;
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ tcg_rmode = tcg_const_i32(float_round_to_zero);
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+ cpu_env);
+ gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+ cpu_env);
+ tcg_temp_free_ptr(fpstatus);
+ tcg_temp_free_i32(tcg_rmode);
+ break;
+ }
case NEON_2RM_VRECPE:
gen_helper_recpe_u32(tmp, tmp, cpu_env);
break;
--
1.8.1.4
